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Intel® 460GX Chipset Software Developer’s Manual 2-41
Register Descriptions
7 EVENT1 Count Enable
If set, then this bit over-rides bits 13:8. If set, then AGP_PMD_0 will count the number
of occurrences of EVENT1 and AGP_PMD_1 will count the number of clocks that
EVENT1 is active. When this bit is not set, then the 2 counters are controlled by bits 13:8.
6:5 Disable Source
Selects event that will disable the performance monitor.
00b Never Disable.
01b Disable when counter overflows.
10b Disable on falling edge of GXB Event 0.
11b Disable on falling edge of GXB Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
00b Never Enable.
01b Enable Always (with this setting, the only meaningful setting for bits 6:5 is 00b).
10b Enable on rising edge of GXB Event 0.
11b Enable on rising edge of GXB Event 1.
2:0 Reload Control.
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload when GXB Event 0 Asserted.
011b Reload when GXB Event 1 Asserted.
100b Reload on GXB Event 0 Asserting edge.
101b Reload on GXB Event 1 Asserting edge.
2.5.4.5 PCI_PMC: PCI Performance Monitor Configuration Register
Function Number: BFN+1
Address Offset: F4h Size: 24 bits
Default Value: 000000h Attribute: Read/Write
Sticky: No Locked: No
The PCI_PMC Register specifies the configuration of the GXB PCI Performance Monitor. This
includes specifying Event Selection, Unit Mask, Enable & Disable Source and Reload Control.
NOTE: the Event Select field determines whether clocks or events are counted. In the case of
events, then all events are counted. In the case of clocks, all clocks in which the selection is active
are counted.
Bits
Description
23:18 reserved(0).
17:16 Initiating Agent
00b reserved.
01b Outbound.
10b Inbound.
11b Selects Both.
15:14 reserved(0).
13:8 Event Select
Selects the event to be monitored.
00 0000b
Monitoring Disabled