Filter
Top Products
Intel® 460GX Chipset Software Developer’s Manual 3-3
System Architecture
New EM code may be weakly ordered. To allow the processor to take advantage of this, the 460GX
chipset defers all reads and returns the data out-of-order to the processor. By returning data in an
out-of-order fashion, the DRAM’s may be accessed in an optimal manner. Accesses are sent out of
the memory queue to free banks of SDRAM’s. Thus, if consecutive addresses are to the same bank,
instead of holding up all later accesses while doing the first 2 in order, later accesses may move
around the second access and allow data to move continuously from SDRAM to the system bus.
To maintain ordering in the system, the processor issues an address and must wait until that address
has been accepted by the system, or in other words become globally visible. If the operation is kept
in the in-order queue, then visibility occurs at the snoop phase with no defer. This means that
operation is not retried and visibility has been met. A read becomes visible when no later store can
change the value seen by the reading processor. A write becomes visible when all later reads will
see the result of that write. With this definition, the 460GX chipset is able to guarantee visibility is
met when the access is deferred, since it prevents any later access from affecting that read. Any
coherent write to that line would be retried until the read is complete. Writes to memory are posted
and so are immediately visible and complete from the system perspective.
There is no ordering relationship between the PCI command streams of an AGP card and its AGP
command streams. The AGP spec mandates certain ordering rules within each stream that are
visible by the graphics card, but the order in which the system does the transactions is not
specified. Therefore, the typical producer-consumer model can not be guaranteed by doing simple
reads and writes across command streams. The AGP card must first issue a “flush” command in
order to guarantee the AGP low-priority stream is observable in memory before sending a flag
(which indicates all the writes are visible to the processor) up the PCI stream.
3.3 Processor to PCI Traffic and PCI to PCI (Peer-to-
Peer) Traffic
Due to the limited number of resources for transactions directed to PCI, a transaction may be
retried if all the resources are utilized. It is possible for one processor or one PCI agent to keep
taking all the resources and preventing a different processor or PCI agent from making any forward
progress.
3.4 WXB Arbitration
The following topics highlight a few of the methods employed within the WXB for starvation
prevention.
3.4.0.1 WXB Arbitration at the PCI Bus
Arbitration for Inbound Transactions
The WXB implements a simple two-level PCI arbitration scheme in the same vein as that of the
PXB-C0. Access to inbound resources is subject to the PCI arbitration scheme and to inbound
resource management algorithms. Inbound Write Request (IWR) acceptance is subject to an IWR
starvation prevention mechanism while Inbound Read Request acceptance is subject to the
availability of either an invalid stream slot or to space in the Delayed Transaction Reservation
Buffer.