Filter
Top Products
Data Integrity and Error Handling
6-6 Intel® 460GX Chipset Software Developer’s Manual
6.5.2 System Bus Errors
There are several errors that are detected by the SAC.
• System Bus Address Parity Error. Parity is checked on both address phases.
— On A[43:24]#, detected by AP[1]#.
— On A[23:3]#, detected by AP[0]#.
• System Bus Request Parity Error. Parity on both phases of the request bus is checked.
— On REQ[4:0]#, detected by RP#.
• Address above TOM. Set for addresses above TOM and not in a PCI range. These addresses
can’t be sent to PCI0, since they may be greater than 4 GB, so are fatal. Out-bound addresses
required a DAC on the PCI bus are not supported and would cause a fault at the xXB.
• Unsupported ASZ#. Since the GX only supports 36bits of address space, accesses which have
ASZ# = 10b or 11b are an error.
• IOQ Underflow/Overflow. This occurs when there are no entries in the IOQ and the SDC
attempts to do a Response Phase. Since the IOQ is empty, there should not be a Response
phase. Or it can occur when either of the following 2 conditions are met: a) when there are 8
entries in the IOQ and a new ADS is seen b) when the IOQ depth is set to 1 for the system and
the IOQ has one entry and a new ADS is seen.
• BERR# Observed#. When the GX sees BERR# active on the bus, whether driven by the
processor or the SAC, it will elevate that to BINIT# if the ‘BERR# to BINIT# Enable’ bit in
CONFIG register is set. If the enable bit is not set, then BERR# is ignored as an input. BERR#
is driven active on the bus for 3 clocks. Each time a new BERR# assertion is sampled, BINIT#
will be driven, unless the error is masked off.
• LOCK# Transaction with No Resources Available. Set when a LOCK# occurs and there are no
outbound resources for the transaction. Since the lock can’t be retried and there is no place to
put the transaction, it gets dropped and lost.
• Resource Counter Overflow/Underflow. Set when the resource counter has an overflow or
underflow. This occurs if there is a retirement to a counter that is empty or a transaction is not
retried when the counter is full.
There is one logging register in the SAC for recording the actual error information. This is
SA_FERR. It captures the system bus address and request for both the a and b phases. This register
can be used to determine which bit is bad on parity errors.
6.5.3 SAC to SDC Interface Errors
The SAC will detect the following errors on the interface between the SDC and the SAC. They are
all flagged in FERR_SAC.
• PDB ITID parity error. Set on a data transfer from SDC to SAC that has bad parity on the ITID
sent with the data.
• Retirement Bus parity error. Set when the SDC attempts to retire an ITID and a parity error
occurs.
• False retirement seen by SAC. Set when the SAC sees a retirement to an ITID that is not in
use.
• ‘Store-Retire’ Command Underflow. Invalid write data sent from SDC to MDC. When the
SDC sends data to the MDC, it signals that it did so to the SAC. This error is flagged when the
‘data-sent’ signal is seen by the SAC, but there are no writes to that stack pending in the SAC.