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Intel® 460GX Chipset Software Developer’s Manual 15-7
PCI/LPC Bridge Description
Thus, any interrupts may be selectively enabled by loading the Mask Register with the appropriate
pattern.
Without Special Mask Mode, if an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the IS bit, the interrupt controller inhibits all lower priority requests. The
Special Mask Mode provides an easy way for the interrupt service routine to selectively enable
only the interrupts needed by loading the Mask register.
The special Mask Mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1,
SMM=0.
15.2.7 Reading the Interrupt Controller Status
The input status of several internal registers can be read to update the user information on the
system. The Interrupt Request Register (IRR) and In-Service Register (ISR) can be read via
OCW3. The Interrupt Mask Register (IMR) is read via a read of OCW1. Here are brief descriptions
of the ISR, the IRR, and the IMR.
Interrupt Request Register (IRR): 8-bit register which contains the status of each interrupt request
line. Bits that are clear indicate interrupts that have not requested service. The Interrupt Controller
clears the IRR’s highest priority bit during an interrupt acknowledge cycle. (Not affected by IMR).
In-Service Register (ISR): 8-bit register indicating the priority levels currently receiving service.
Bits that are set indicate interrupts that have been acknowledged and their interrupt service routine
started. Bits that are cleared indicate interrupt requests that have not been acknowledged, or
interrupt request lines that have not been asserted. Only the highest priority interrupt service
routine executes at any time. The lower priority interrupt services are suspended while higher
priority interrupts are serviced. The ISR is updated when an End of Interrupt Command is issued.
Interrupt Mask Register (IMR): 8-bit register indicating which interrupt request lines are masked.
The IRR can be read when, prior to the I/O read cycle, a Read Register Command is issued with
OCW3 (RR=1, RIS=0).
The ISR can be read when, prior to the I/O read cycle, a Read Register Command is issued with
OCW3 (RR=1, RIS=1).
The interrupt controller retains the ISR/IRR status read selection following each write to OCW3.
Therefore, there is no need to write an OCW3 before every status read operation, as long as the
current status read corresponds to the previously selected register. For example, if the ISR is
selected for status read by an OCW3 write, the ISR can be read over and over again without writing
to OCW3 again. However, to read the IRR, OCW3 will have to be reprogrammed for this status
read prior to the OCW3 read to check the IRR. This is not true when poll mode is used. Polling
Mode overrides status read when P=1, RR=1 in OCW3.
After initialization the Interrupt Controller is set to read the IRR.
As stated, OCW1 is used for reading the IMR. The output data bus will contain the IMR status
whenever I/O read is active the address is 021h or 061h (OCW1).
15.2.8 Interrupt Steering
The IFB can be programmed to allow 4 PCI programmable interrupts (PIRQA#-PIRQD#) to be
internally routed to one of 11 interrupts: 3 - 7, 9-12, 14 or 15. PCLK is used to synchronize the
PIRQx# inputs. The PIRQx# lines are run through an internal multiplexer that assigns, or routes, an