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Register Descriptions
2-6 Intel® 460GX Chipset Software Developer’s Manual
Bits Description
7 Disable
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
6 Valid
If set then the ITID in bits 5:0 is valid and shows the address of a single-bit memory error.
Writing a 1 to this bit will clear the ITID and reset the valid bit.
5:0 ITID
The ITID of the SEC error. These bits are read-only.
2.4.1.2 DEDTID: DED ITID
Bus CBN, Device Number: 00h Function: 0
Address Offset: 81h Size: 8 bits
Default Value: 00h Attribute: Read Only/Write
Clear, Read/Write
Sticky: Yes Locked: No
This register is used to capture the ITID for a double bit memory ECC error. The ITID can then be
used to determine the address of the failure. To force the ITID to be cleared and re-used, write a 1
to bit 6. This register is set anytime that the DED bit is sent from the SDC to the SAC on a ‘Retire
ITID’ command.
Bits
Description
7 Disable
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
6 Valid
If set then the ITID in bits 5:0 is valid and shows the address of a double-bit memory
error. Writing a 1 to this bit will clear the ITID and reset the valid bit.
5:0 ITID
The ITID of the double-bit error. These bits are read-only.
2.4.1.3 FSETID: FSE ITID
Bus CBN, Device Number: 00h Function: 0
Address Offset: 82h Size: 8 bits
Default Value: 00h Attribute: Read Only/Write
Clear, Read/Write
Sticky: Yes Locked: No
This register is used to capture the ITID for a system bus data error. The ITID can then be used to
determine the address of the failure. To force the ITID to be cleared and re-used, write a 1 to bit 6.
This register is set anytime that the ADE bit is asserted and both SEC and DED are deasserted on a
’Retire ITID’ command from the SDC to the SAC. NOTE: this register is set for both processor-
bus errors and errors on the SAC-to-SDC data bus.