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Register Descriptions
2-42 Intel® 460GX Chipset Software Developer’s Manual
00 0010b All PCI Clocks
00 0100b Idle Bus Cycles
00 0111b All Disconnect Events
00 1000b Lock Asserted Clocks
00 1001b Lock Asserted Events
00 1011b I/O Reads - Events
00 1101b I/O Writes - Events
00 1111b Memory Read Events
01 0001b Memory Write Events
01 0011b SRAM Read Events
01 0101b SRAM Write Events
01 0111b Write Combining Events
01 1000b WBF# Active - Clocks
01 1001b WBF# Active - Events
01 1011b Retry Read that’s not Delayed - Events
01 1101b Retry Write because no Write Slot available - Events
01 1110b Count PCI clocks waiting (Devsel and !IRDY and TRDY)
10 0000b Count PCI clocks waiting (Devsel and IRDY and !TRDY)
10 0010b Count PCI clocks data is transferring
7 reserved(0).
6:5 Disable Source
Selects event that will disable the performance monitor.
00b Never Disable.
01b Disable when counter overflows.
10b Disable on falling edge of GXB Event 0.
11b Disable on falling edge of GXB Event 1.
4:3 Enable Source
Selects event that will enable the performance monitor.
00b Never Enable.
01b Enable Always (with this setting, the only meaningful setting for bits 6:5 is 00b).
10b Enable on rising edge of GXB Event 0.
11b Enable on rising edge of GXB Event 1.
2:0 Reload Control
Selects event that will control the Reloading of the performance monitor with the value
written into the associated PMD register.
000b Never Reload.
001b Reload when counter overflows.
010b Reload on GXB Event 0 Asserted.
011b Reload on GXB Event 1 Asserted.
100b Reload on GXB Event 0 Asserting edge.
101b Reload on GXB Event 1 Asserting edge.