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AGP Subsystem
7-10 Intel® 460GX Chipset Software Developer’s Manual
Delayed transactions are issued and serviced as follows:
1. Upon receiving a read request, the address is compared against the GXB’s internal buffers.
Unless the data corresponding to this request is already available in the buffers (i.e. from a
previously retried request), the read cycle is immediately retried (the GXB retries the read
cycle in three PCI clocks from FRAME# driven active).
2. If there is an available Delayed Transaction Request buffer (there is only one per GXB), then
the GXB will latch the pertinent information and forward the read request.
3. When the data is returned, the GXB will store it in its internal buffers, and flag the buffers as
“available” for a subsequent read to that address (i.e. GOTO #1).
The GXB allows only one outstanding Delayed Transaction access. After accepting a Delayed
Transaction, the GXB maintains system concurrency by continuing to accept and process
additional writes as buffering allows. If the Delayed Transaction Request slot is full, the GXB will
retry all reads that do not match the address and byte enables of the pending Delayed Transaction.
For PCI Stream AGP to DRAM writes, the GXB will post the cycle unless the posted write slots
are full (in which case the write is retried).
The GXB does not differentiate between read transactions from different masters. If a different
master, other than the one that initiated the Delayed Transaction, attempts to read the same DRAM
location as the Delayed Transaction, the GXB will respond with the data and complete the Delayed
Transaction on the AGP bus.
7.2.7.2 PCI Stream Read Prefetching
The GXB delays all inbound reads. A Memory Read targeting memory will fetch 8B, unless the
transaction begins 4B from the end of a cache line, in which case the transaction only fetches 4B. A
Memory Read Line or Memory Read Multiple will always prefetch up to one cache line of data.
When the read data is available in the GXB, the next matching read attempt from the controller is
accepted and the data is streamed to the AGP bus until the controller disconnects or the prefetched
data is consumed. Any data left when the controller disconnects is discarded. If the controller
disconnects half way through a line, and comes back with the next address; then a new read is sent
to DRAM for the data.
7.2.7.3 Inbound Reads Directed To Memory
All PCI reads-to-memory are propagated up through the SAC and placed on the system bus to
allow snooping. The snoops are performed using the Memory Read (Length=0) transaction, which
does not transfer data on the system bus. Instead, the data is transferred directly from the memory
to the SAC, and finally back to the GXB. This path means that PCI Stream AGP-DRAM reads
need consume no host data bus bandwidth (except in the case of implicit writebacks).
Note: The GXB as a PCI target supports only a linear incrementing burst (denoted by AD[1:0]=00 during
the address phase). A PCI burst request specifying any type of sequence other than linear results in
a disconnect after the first data phase.
7.2.7.4 Inbound Delayed Read Matching Rules
The completion response returned to the GXB for a Delayed Read transaction is matched to the
requesting PCI master by using information that was latched into the target during the initial
request. This information consists of the address, command and byte enables. Table 7-2 illustrates
which read request information is used for matching Delayed Read Completions to the requesting
agent.