Filter
Top Products
Intel® 460GX Chipset Software Developer’s Manual 2-7
Register Descriptions
Bits Description
7 Disable
This bit can be written by software. When set, the ITID is retired immediately and not
captured. Therefore there can be no checking of the address. See Section 6 for the usage
of this bit.
6 Valid
If set then the ITID in bits 5:0 is valid and shows the address of a system bus data error.
Writing a 1 to this bit will clear the ITID and reset the valid bit.
5:0 ITID
The ITID of the system bus error. These bits are read-only.
2.4.1.4 FERR_SAC: First Error Status Register
Bus CBN, Device Number: 00h Function: 1
Address Offset: 40h Size: 32 bits
Default Value: 000000h Attribute: Read/Write Clear
Sticky: Yes Locked: No
This register records the first error condition detected in the SAC/SDC.
Bits
Description
31 Memory Card B Error (MBE)
Set when the memory card B signals a fatal error.
30 Memory Card A Error (MAE)
Set when the memory card A signals a fatal error.
29 XSERR# Asserted (XSA)
Set when the SAC sees the signal XSERR# active.
28 ‘Store-Write’ Command Underflow, card A, Stack L (SCAL)
27 ‘Store-Write’ Command Underflow, card A, Stack R (SCAR)
26 ‘Store-Write’ Command Underflow, card B, Stack L (SCBL)
25 ‘Store-Write’ Command Underflow, card B, Stack R (SCBR)
One of these 4 is asserted when a signal is sent from the SDC to the SAC indicating write
data was sent to the MDC, and there is no outstanding write in the SAC.
24 SDC Correctable Memory Error (SCME)
Reports correctable DRAM errors (single-bit ECC errors). This bit does not mask other
bits in the FERR register from being set. It is the one exception to the rule that only one
bit in FERR may be set at a time.
23 SDC Non-Fatal Error (SNE)
Reports non-fatal errors that are uncorrectable such as double-bit ECC error, or parity
errors. This also reports a single-bit correctable error on the system bus. This bit will also
be set if there is a second correctable error from memory in the SDC, and the first one has
not been cleared by the time the second one occurs. The first correctable memory error
would have set the SCME bit, and all later correctable memory errors (until the SDC’s
error registers are cleared) are reported as SNE in the FERR or NERR.
22 SDC Fatal Error (SFE)
Fatal error in SDC.
21 ‘Completion’ Command Underflow; MAC A, Stack L (CCAL)
20 ‘Completion’ Command Underflow; MAC A, Stack R (CCAR)
19 ‘Completion’ Command Underflow; MAC B, Stack L (CCBL)