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Intel® 460GX Chipset Software Developer’s Manual 2-43
Register Descriptions
2.5.5 WXB
2.5.5.1 PCI_WXB_PMC0: PCI Performance Monitor Configuration Register
Address Offset: DCh – DFh Size: 32bits
Default Value: 00000000h Attribute: Read/Write
This register controls the PCI performance monitors. There are two performance monitors for each
PCI bus. This register defines the events to be monitored, and when monitoring should start and
stop. The selected event can be qualified by data transferred, and issuing agent.
Bits
Description
31:24 reserved (0)
23:21 Data Transfer and Transaction Qualifier
Qualifies a selected “Packet Type” by the presence or absence of data transferred.
000bAll events
001bRetry - for any reason
010bRetry - no buffers available (inbound read or write transactions only)
011bRetry - no data available (inbound read transactions only)
101bLocked
110bDual Address Cycles
20:19 reserved (0)
18:17 Issuing Agent Qualifier
Monitor only those selected events issued by the following agent:
00breserved
01bOutbound: Issued by WXB
10bInbound: Not issued by WXB
11bAll: Issued by any agent
16:11 Event Select
Selects the event(s) to be monitored.
Measurement
00 0000b Monitoring Disabled
Transaction Types
01 0001bI/O Reads
01 0010bMemory Reads
01 0100bMem Read Lines
01 1000bMem Read Multiples
01 1111bAny Read
10 0001bI/O Writes
10 0010bMemory Writes
10 0100bMem Wr & Invalidates
10 1111bAny Write
11 1111bAny Transaction
10:4 reserved (0)
3 Enable Source
When this bit is set to 1, the performance monitoring logic is enabled. Default=0.
2:0 reserved (0)