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WXB Hot-Plug
8-10 Intel® 460GX Chipset Software Developer’s Manual
8.1.21 Arbiter SERR Status
Address Offset: 4A Size: 8 bits
Default Value: 00h Attribute: Partial Read/Write
Bits
Description
7:0 reserved (0)
8.1.22 Memory Access Index
Address Offset: 50h-53h Size: 32 bits
Default Value: 00000000h Attribute: Partial Read/Write
When the “Enable PCI Config Space Access to Hot-Plug Registers” bit in the Miscellaneous Hot-
Plug Configuration Register is set, this register becomes a pointer into the IHPC memory mapped
register space (divided into 64, 32-bit Dwords).
Bits
Description
31:8 reserved (0)
7:2 Hot-Plug Memory Access Index
Read/Write
1:0 reserved (0)
8.1.23 Memory Mapped Register Access Port
Address Offset: 54h-57h Size: 32 bits
Default Value: 00000000h Attribute: Read/Write
When the “Enable PCI Config Space Access to Hot-Plug Registers” bit in the Miscellaneous Hot-
Plug Configuration Register is set, this register becomes mapped into the IHPC memory mapped
register space at the location pointed to by the Memory Index Register.
Bits
Description
31:0 Memory Mapped Register Access Port
8.2 IHPC Memory Mapped Registers
Each IHPC reserves 256 bytes of memory mapped registers. A list of those registers follows.
Unlike other register descriptions in this document, the offset listed is always Dword aligned with
bit offset provided. This nomenclature is used to be consistent with the Memory Access Index
Register in IHPC configuration space. The default power-up value is included in each register
description heading.