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System Architecture
3-2 Intel® 460GX Chipset Software Developer’s Manual
For WC memory, one processor may write to an address that is marked WC in its page table and
hold the write in its own data buffer, while waiting to write to the bus. If a different processor were
to read this address, the first processor does not snoop the WC holding registers and therefore
would not provide the newly written data. So the 2nd processor would get the data from memory
which is stale or un-updated with respect to the first processor.
Processor caches use physical addresses for indexing into the cache. The memory attributes are
marked in the page tables which are based on the virtual address. If the O/S points two virtual
addresses to the same physical page and provides different attributes for each, then coherency may
not be maintained between processors, since one may have used the virtual address that pointed to
the page as WB and the other one used a different virtual address that pointed to the same physical
page, but was marked WC. This is usually considered a programming error. It may be useful in
some applications, but software takes full responsibility for the results.
3.1.2 PCI Coherency
As well as processor to processor coherency, the I/O subsystem maintains coherency between
processor caches and transactions initiated on PCI or other I/O devices that are directed to memory.
This is done in hardware and therefore software is not required to flush caches before I/O
operations (as long as that page is not marked WC).
Reads originating from the I/O sub-system are presented to the system bus for snooping. If a
processor has the modified (dirty) data, then it provides it on the data bus and the SAC presents this
data back to I/O. If no cache has the data modified, then the data is provided by the SDRAMs.
Writes are presented to the system bus as well. This allows a new code or data page to be brought
in and the old page to be invalidated as the write is being done for each line. Writes may get a
HITM# snoop which causes the processor to write back the entire line and then having the I/O
write to overwrite the particular bytes it wishes to update.
3.1.3 AGP Coherency
AGP transactions originate from a graphics (or other) device residing in the one AGP slot provided
when using the GXB. There are 2 different types of transactions originating from a device in this
slot. The graphics card may do coherent or non-coherent transactions.
Non-coherent transactions are not required to be placed on the system bus (although they could be,
with some loss of bus bandwidth). The 460GX chipset implementation does not pass non-coherent
AGP traffic to the system bus. These addresses are sent directly to the memory queue. The
processor could still have these addresses cached. If the application wishes to do this, then it must
handle coherency itself. Software must flush the processor’s cache.
Coherent traffic from the graphics card is treated like coherent PCI traffic. Addresses are sent to the
system bus before being serviced by the memory system.
3.2 Ordering
Intel processors prior to the Itanium processor have used processor consistency for their ordering
model. The Itanium processor allows both a strongly ordered and a weakly ordered programming
model to be implemented.