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PCI/LPC Bridge Description
15-6 Intel® 460GX Chipset Software Developer’s Manual
15.2.5 Edge and Level Triggered Mode
This mode is programmed using bit 3 in ICW1. With IFB this bit is disabled and a new register for
edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2. The default programming is equivalent to programming the
LTIM bit (ICW1 bit 3) to a 0 (all interrupts selected for edge triggered mode). Note, that IRQ0, 1,
2, 8#, and 13 can not be programmed for level sensitive mode and can not be modified by software.
If an ELCR bit = “0”, an interrupt request will be recognized by a low to high transition on the
corresponding IRQx input. The IRQ input can remain high without generating another interrupt.
If an ELCR bit = “1”, an interrupt request will be recognized by a high level on the corresponding
IRQ input and there is no need for an edge detection. The interrupt request must be removed before
the EOI command is issued to prevent a second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling
edge of the first INTA#. If the IRQ input goes inactive before this time, a default IRQ7 will occur
when the CPU acknowledges the interrupt. This can be a useful safeguard for detecting interrupts
caused by spurious noise glitches on the IRQ inputs. To implement this feature, the IRQ7 routine is
used for “clean up” simply executing a return instruction, thus ignoring the interrupt. If IRQ7 is
needed for other purposes, a default IRQ7 can still be detected by reading the ISR. A normal IRQ7
interrupt will set the corresponding ISR bit; a default IRQ7 will not set this bit. If a default IRQ7
routine occurs during a normal IRQ7 routine, however, the ISR will remain set. In this case, it is
necessary to keep track of whether or not the IRQ7 routine was previously entered. If another IRQ7
occurs, it is a default.
15.2.6 Interrupt Masks
15.2.6.1 Masking on an Individual Interrupt Request Basis
Each interrupt request input can be masked individually by the Interrupt Mask Register (IMR).
This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel, if it
is set to a 1. Bit 0 masks IRQ0, Bit 1 masks IRQ1 and so forth. Masking an IRQ channel does not
affect the other channel's operation, with one exception. Masking IRQ2 on CNTRL-1 will mask off
all requests for service from CNTRL-2. The CNTRL-2 INTR output is physically connected to the
CNTRL-1 IRQ2 input.
15.2.6.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the system priority
structure during its execution under software control. For example, the routine may wish to inhibit
lower priority requests for a portion of its execution but enable some of them for another portion.
The difficulty is that if an Interrupt Request is acknowledged and an End of Interrupt command did
not reset its IS bit (i.e. while executing a service routine), the Interrupt Controller would have
inhibited all lower priority requests with no easy way for the routine to enable them.
The Special Mask Mode enables all interrupts not masked by a bit set in the Mask Register.
Interrupt service routines that require dynamic alteration of interrupt priorities can take advantage
of the Special Mask Mode. For example, a service routine can inhibit lower priority requests during
a part of the interrupt service, then enable some of them during another part.
In the Special Mask Mode, when a mask bit is set to 1 in OCW1, it inhibits further interrupts at that
level and enables interrupts from all other levels (lower as well as higher) that are not masked.