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Intel® 460GX Chipset Software Developer’s Manual 6-7
Data Integrity and Error Handling
The SDC will capture the following errors on its side of the interface.
• PDB Data Parity Error. On data received from the SAC, parity is checked. If parity is bad, the
data is sent to memory or the system bus with poisoned ECC.
• PDB Byte Enable Parity Error. On parity errors for the byte enables, the entire data transfer is
sent to memory or the system bus with bad ECC. If the transfer is 64B then the entire line will
have bad ECC.
• PDB Command Parity Error. Parity is checked over the Command bus from the SAC to SDC.
• PDB ITID Parity Error. Parity is checked on the ITID bus which accompanies the data from
the SAC. The data is dropped.
• PDB Receive Length Error. Occurs when the SDC receives data and the length of the data
transfer doesn’t match the length indicated by the command for that transfer.
• Configuration Information Parity Error. Config accesses from the SAC to the SDC go through
the data buffer in the SDC for both the address and data of the targeted register. Parity errors
on reading out either the address or data from the buffer are detected.
6.5.4 SAC to MAC Interface Errors
The SAC will detect the following errors on the memory card interface.
• Completion Command Underflow. When the MAC has completed a transaction (either a read
or a write), it will send a ‘Complete’ back to the SAC. Since each stack is kept ordered, the
SAC can pop the top of the queue for the stack sending the ‘Complete’. This error is flagged
when the stack queue is empty and a ‘Complete’ is received for that stack.
The MAC will detect the following error in its interface with the SAC.
• Memory Card Error. This is set on a parity error on the command sent from the SAC. The
command bus is a 23 bit bus (22 address bits and one parity bit). This error is flagged in the
MAC when there is bad parity on this bus. The bus should always be driven with good parity.
Parity checking is done every cycle. The MAC will complete any outstanding transactions, i.e.
those with RAS already started. It will not start any new transactions for either stack until it is
reset. Refreshes will continue, though no new accesses will start until the MAC is reset. The
error is signaled to the system on the MAC’s ERR# pin, which sets FERR_SAC [MAE or
MBE].
6.5.5 SDC/Memory Card Interface Errors
The following errors are detected.
• Card x SEC. Data corrected and placed into the data buffer.
• Card x DED. Data placed into the data buffer with bad parity on each chunk that had bad ECC.
Data is sent to the system bus with poisoned ECC or to the PDB with bad parity.
• ‘Accept’ Underflow. Set when the SDC received data from the memory card without having
an ‘Accept’ command pending.
• ‘Forward’ Underflow. Set when the SDC receives a Forward signal from the MAC without a
corresponding ‘Store’ command.
• ‘Forward’ Overlapping ‘Forward’. Set when the SDC is doing a ‘Forward’ by sending data
and then another ‘Forward’ is seen before the first finishes. The SDC does not queue up these
commands and the timings would imply that two lines are being transferred at the same time.
• ‘Load’ overlapping ‘Load’. Set when the SDC is doing a ‘Load’ by receiving data and a
second ‘Load’ is seen before the first ‘Load’ finishes. This implies the MDC is sending data
for two different lines at the same time.