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Data Integrity and Error Handling
6-32 Intel® 460GX Chipset Software Developer’s Manual
• MWI to a misaligned (non-cache-line-boundary) address
• MWI to an aligned address, but with one or more byte enables not asserted
Refer to the PCI specification for a complete description of the required PCI protocol.
6.12.8.3 PCI Interface Errors
Other PCI interface errors that are handled by the WXB are:
• System Error Signaled
Set within the FEPCI register when the WXB sees an SERR# asserted by another PCI agent.
This is not set when the WXB drives SERR#.
• Discard Timer Expiration
Set when the 2
15
timer expires. The timer starts approximately when the data for a delayed
read is requested by the WXB. If the card doesn’t re-access the data in 2
15
PCI clocks, then an
error is flagged.