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AGP Subsystem
7-6 Intel® 460GX Chipset Software Developer’s Manual
For all AGP-type accesses which hit in the AGP range, there is a bit per GART entry which
determines whether the address is coherent. For AGP-type accesses outside the AGP range, there is
a bit in a configuration register of the GXB which determines the coherency. Coherency or non-
coherency applies to accesses using AGP protocol only. Accesses using PCI protocol are always
done coherently, whether they hit the translation table or not.
Accesses using AGP protocol which are non-coherent are truly not coherent. There is no ordering
between them and processor traffic at all. The traffic goes directly to memory regardless of
processor cache state or bus locks. However accesses within the AGP stream must follow the AGP
ordering rules regardless of whether or not they are coherent. Coherent low-priority writes will
push non-coherent low-priority writes, as the AGP spec calls for. Coherent traffic is not a separate
stream from non-coherent traffic within the GXB.
7.1.4.1 3.3V AGP 1X and 2X Mode Compatibility
The GXB will be compatible with 3.3V AGP 1X and 2X mode cards. If they do accesses of less
than 32 bytes, then their performance may not be adequate. As well, some AGP cards might expect
lower latencies than the 460GX chipset will guarantee. These cards must not have a watchdog
timer or other time-out mechanism which requires a latency lower than the 460GX chipset is able
to guarantee.
7.1.5 Interrupt Handling
Before an interrupt is delivered to the processor, the system must ensure visibility or completion of
all operations from that device which were generated before that interrupt. For PCI, device drivers
are required to read a status register on the card that caused the interrupt. If the card had done a
write before the interrupt, then the read completion would force the write to have been seen by the
system.
AGP, with its hi-priority, low-priority and PCI streams, has no concept of ordering between the
streams. Therefore reading an AGP cards register will not enforce pending hi or low-priority writes
to have been completed. If the graphics card needs to force all writes to be visible to the system
before the interrupt is visible, then the AGP card must issue a flush operation to guarantee that all
writes are complete, wait for the return of the flush acknowledgment, and then issue the interrupt.
Even using Itanium processor’s SAPIC interrupt protocol, whereby a write on the PCI bus
becomes an interrupt to the processor, does not guarantee that writes from other streams have
become visible to the system by the time the interrupt is received.
The interrupt signals on the AGP 4X mode interface will be routed to an I/O APIC chip (PID).
The GXB will not receive these signals. The GXB will have an interrupt pin that it will drive for
error reporting.
7.2 AGP Traffic
7.2.1 Addresses Used by the Graphics Card
AGP introduced the concept of a contiguous virtual address range that the graphics card could use.
This address range lies outside the physical memory space. It also lies outside the range of
addresses mapped to I/O. This range may exist in one of two places in the 460GX chipset system
map. The virtual address is limited to 40 bits for the GXB, even when in 64-bit addressing mode.