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SILICON GATE MOS 8702A
A.C. CHARACTERISTICS
TA =
00
C
to
+70°C, V
cc
=+5V ±5%, V
oo
=
-9V
±5%, V
GG
=
-9V
±5% unless otherwise noted
SYMBOL
TEST
MINIMUM
TYPICAL
MAXIMUM
UNIT
Freq. Repetition Rate
1
MHz
tOH
Previous
read
data
val
id
100
ns
tAcc
Address
to
output
delay
1.3
p.s
t
ovGG
Clocked V
GG
set
up
[2]
1.0
JlS
t
es
Chip select delay
400
ns
teo
Output
delay
from
CS
900
ns
too
Output
deselect
400
ns
tOHC
Data
out
hold
in
clocked V
GG
mode (Note
1)
5
JlS
Note
1.
The
output
will
remain
valid
for
tOHe
as
long
as
clocked
VGG
is
at
Vee.
An
address
change
may
occur
as
soon
as
the
output
is
sensed
(clocked
VGG
may
still
be
at
Vee).
Data
becomes
invalid
for
the
old
address
when
clocked
VGG
is
returned
to
VGG.
2.
For
this option please specify 8702AL
CAPACITANCE*
SYMBOL
TEST
MINIMUM
TYPICAL
MAXIMUM
UNIT
CONDITIONS
C
1N
I
nput
Capacitance
8
15
pF
'1N=
Vee }
All
C
OUT
Output
Capacitance 10
15
pF
CS
=V
ce
unused pins
C
VGG
V
GG
Capacitance
30
pF
V
OUT
=
Vee
are
at A.C.
(Clocked V
GG
Mode)
V
GG
=V
ce
ground
~
This
parameter
is
periodically sampled and
is
not
100% tested.
~~Ons
L·'·';
I I
I
\--
-
---:
I
tOD~
~50ns
I
NOTE
2
-,
,,,r---;;.
.....
---7
DATA
OUT
B)
Clocked V
GG
Operation
'-
CYCLE:
TIME
- 1
FREO
~
VIHXI,0"lo
xl
ADDRESS
~
I
._
90%
• •
V
1L
I------------..J
I~---
I 1
Cs
'
VIH
\1
1
1 :
I---~Ons_____'
I
V
1L
\1--------11----------
-I
I.-
t
DV
:
Vcc\~
:
GG
J
CLOCKED
"I
/:
V
GG
Vee;
I:
: (SEE
NOTE
11
r----
tACC
----i
-I
~.
'OHC
I I
I I
I I
DATA
~~~:
\
{'
:.-
tACC
---\
VOl~
•
..J
NOTE
1:
The
output
will
remain
valid
tor
tOHe
as
long
as
clocked
VGG
is
at
Vee.
An
address
change
may
occur
as
soon
as
the
output
is
sensed
(clocked
VGG
may
still
be
at
Vee!.
Data
becomes
invalid
for
the
old
address
when
clocked
VGG
is
returned
to
VGG'
~OTE
2:
It
CS
makes
a
transition
from
VI
L
to
VIH
while
clocked
VGG
IS
at
VGG.
then
deselection
of
output
occurs
at
too
as
shown
in
static
operation
with
constant
VGG.
V
,H
v:
DESELECTIDN OF DATA OUTPUT
IN
DR·TlE OPERATION
ADDRESS
.A
V
1L
1-----------------
I
I
CS
V
,H
'\
V
1L
I
~~t
V
CC
,\':
DV
GG
CLOCKED
::
/
V
GG
I
V
GG
I
"tl------JI
I
I
V
OH
7-
DATA
l
OUT
I
V
1H
){~10%
--XI
ADDRESS
I
~
90%
V
1l
I
.....
------------J,
.......
----
----I t
cs
~
I
_ V
1H
ill
t--
toH--1
cs I I
':
V
1l
: I
I
I
I
,
CYCLE
TIME
I/F
REO
V
1H
---f
10%
cs
V
1l
I
V
OH
---fe'
I
- too -
I
V
DATA
I
OUT
I
VOL
I
-l
teo
f-
Conditions
of
Test:
Input pulse amplitudes: 0
to
4V;
t
R
'
t
F
::;
50
ns
.
Output load
is
1
TTL
gate; measurements
made
at
output
of
TTL
gate
(t
pD
~
15
ns)
A) Constant V
GG
Operation
SWITCHING CHARACTERISTICS
5-39