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SILICON GATE MOS 8102A-4
A.
C.
Characteristics T
A
= O°C
to
70°C,
Vee = 5V
±5%
unless otherwise specified
Limits
Symbol
Parameter
TypJ1 ]
Unit
Min.
Max.
READ
CYCLE
tRC
Read
Cycle
450
ns
tA
Access Time
450
ns
tco
Chip Enable
to
Output
Time
230
ns
tOHl
Previous Read Data Valid with Respect
to
Address
40
ns
tOH2
Previous Read Data Valid with Respect
to
Chip Enable 0
ns
WRITE
CYCLE
twc
Write Cycle
450
ns
tAW
Address
to
Write Setup Time
20
ns
twP
Write Pulse Width
300
ns
tWA
Write Recovery Time
0
ns
tow
Data Setup Time
300
ns
tOH
Data Hold Time
0
ns
tcw
Chip Enable
to
Write Setup Time
300
ns
NOTE:
1.
Typical
values are
for
TA
= 25°C and
nominal
supply
voltage.
Capacitance
l21
T
A
= 25°C, f = 1MHz
A. C. CONDITIONS
OF
TEST
Input
Pulse Levels:
0.8
Volt
to
2.0
Volt
Input
Rise and Fall Times: 10nsec
Timing
Measurement Inputs: 1.5
Volts
Reference Levels
Output:
0.8
and
2.0
Volts
Output
Load: 1
TTL
Gate!
and
CL
=
100
pF
SYMBOL
TEST
LIMITS
(pF)
Typ.,[1]
MAX.
C
1N
INPUT CAPACITANCE
3
5
(ALL
INPUT PINS) V
1N
=:
OV
C
OUT
OUTPUT CAPACITANCE
7
10
V
OUT
=
OV
NOTE:
2.
This parameter
is
periodically
sampled
and
is
not
100% tested.
Waveforms
READ CYCLE WRITE CYCLE
tRC
twe
ADDRESS
CD
teo
CHIP
CHIP
'ew
ENABLE
ENABLE
tA
twP
DATA
READI
OUT
WRITE
CD
1.5
VOLTS
tow
®
2.0 VOLTS
fj)
0.8 VOLTS
DATA DATA
CAN
DATA
STABLE
IN
CHANGE
5-81