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SILICON GATE MOS 8080A-1
A.C. CHARACTERISTICS (Continued)
T
A
=
O°C
to
70°C,
Vo
o
=
+12V
± 5%,
Vee
=
+5V
±
5%,
Vss
=
-5V
± 5%, V
ss
= OV, Unless Otherwise
Noted
Symbol
Parameter
Min.
Max.
Unit
Test
Condition
tOS2
Data Setup
Time
to
¢2
During
DBIN
120
nsec
tOH
[1]
Data
Hold
Time
From
¢2
During
DBIN
[1]
nsec
tiE [2]
INTE
Output
Delay
From
¢2
200
nsec
CL
=
50pf
tRS
READY
Setup
Time
During
¢2
90
nsec
tHS
HOLD
Setup
Time
to
¢2
120
nsec
tiS
INT
Setup
Time
During
¢2 (During
<t>1
in
Halt
Mode)
100
nsec
tH
Hold
Time
From
¢2
(REAOY,
INT,
HOLD)
0
nsec
tFO
Delay
to
Float
During
Hold
(Address
and
Oata
Sus)
120 nsec
tAW [2]
Address Stable
Prior
to
WR
........,
[5]
nsec
tOW[2]
Output
Data Stable
Prior
to
WR
[6]
nsec
two
[2]
Output
Data Stable
From
WR
[7] nsec
tWA[2]
Address Stable
From
WR
[7]
nsec
~
CL
=
50pf:
Address, Data
CL
=50pf:
WR,
HLDA,
DBIN
tHF[2]
H
LDA
to
Float
Delay
[8]
nsec
tWF[2]
WR
to
Float
Delay
[9]
nsec
tAH [2]
Address
Hold
Time
After
DBIN
During
HLDA
-20
nsec
-
NOTES:
1. Data
input
should be enabled
with
OBIN
status.
No
bus
conflict
can
then
occur
and
data
hold
time
is
assured.
tOH
::::
50
ns
or
tOF,
whichever
is
less.
2.
Load
Circuit.
+5V
9
+100
2.1K
+50
~
CAPACITANCE
(pf)
(CACTUAL
- C
SPEC
)
o
-50
.5-
>
+10
~
...J
W
0
~
0
::::>
Q.
~
::::>
-10
0
-1
3. tCY::::
t03
+ t
n
t>2
+
t4>2
+
tf4>2
+
t02
+ t
r
4>1
;> 320ns.
8080A
OUTPUT
TYPICAL!:J.
OUTPUT
DELAY
VS.
~
CAPACITANCE
+20
r-------.-----------r----
-----,
A
1S
-A
O
~
twA
0
7
-0
0
I-
-
two
SYNC
oBIN
WR
t
oc
READY
WAIT
HOLD
I-
HLoA
INT
INTE
---.
t
oc
.--
4.
The
following
are relevant when
interfacing
the
8080A
to
devices having
VIH
::::
3.3V:
a)
Maximum
output
rise
time
from
.8V
to
3.3V
=1
OOns
@
CL
=SPEC.
b)
Output
delay when measured
to
3.0V
=SPEC +60ns @
CL
=SPEC.
c)
If
CL
:f. SPEC, add .6ns/pF
if
CL>
CSPEC, subtract
.3ns/pF
(from
modified
delay)
if
CL
<CSPEC.
5. tAW:::: 2
tCY
-t03
-t
n
t>2
-110nsec.
6.
tOW::::
tCY
-t03
-t
r
</>2
-150nsec.
7.
If
not
HLDA,
tWO:::: tWA::::
t03
+ t
r
<P2
+10ns.
If
HLOA,
tWO::::
twA
::::
tWF.
8. tHF
::::
t03
+t
r
<P2
-50ns.
9.
tWF =
t03
+t
r
4>2
-10ns
10. Data in must be stable
for
this
period
during
DBIN
·T
3.
Both
tOS1 and tOS2 must be satisfied.
11. Ready signal must be stable
for
this
period
during
T2
or
TW. (Must be
externally
synchronized.)
12.
Hold
signal
must
be stable
for
this
period
during
T2
or
TW
when entering
hold
mode, and
during
T3, T4,
TS
and TWH when
in
hold
mode. (External
synchronization
is
not
required.)
13.
Interrupt
signal
must
be stable
during
this
period
of
the
last
clock cycle
of
any instruction
in
order
to
be
recognized
on
the
following
instruction.
(External
synchronization
is
not
requiredJ
14. This
timing
diagram shows
timing
relationships
only;
it
does
not
represent any
s~ific
machine cycle.
5-23