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Schottky Bipolar
8222
DYNAMIC MEMORY
REFRESH CONTROLLER
BLOCK
DIAGRAM
• Internal Address
Multiplexer
• Up
to
6 Ro .
(64x
64,t}'
'\ff
PIN
CONFIGURATION
• Adjustable Refresh
Request Oscillator
• Ideal
for
8107A,
81078
4K
RAM
Refresh
START
CYCLE
CYC. REQ.
REFRESH
ACK
BUSY
REQUEST
REF.
ON
a
LOGIC
REFREQ
CYREQ
STARTCY
ADDRESS INPUT A
2
CENTER
ADDRESS INPUT A
1
OUTPUT
ADDRESS INPUT A
o
A
4
ADDRESS INPUT
MUX
ADDRESSES
INPUT
Ao-A
s
ADDRESS OUTPUT
00
As ADDRESS INPUT
ADDRESSES
ADDRESS OUTPUT 0
1
Vee
ADDRESS OUTPUT
02
04
ADDRESS OUTPUT
cX/Rxl---
REF.
GROUND
03
ADDRESS OUTPUT
REa.
D
osc.
I
-=-
The 8222
is
a refresh controller for dynamic
RAMs
requiring row
ref.JJj"\:;;
W
inR,~"addresses
(or
4K
bits for 64 x
,'<:i"~:/:,
0 ,
~
'~
64 organization). The device contains an accurate refresh timer
(w~~)t::,~rL,
,"
'"
n
be,,-set
by an external resistor and ca-
,:~\~'r',;":::--:,
0,<,:,,,:-,:<':). ,
.:-~~
pacitor) plus
all
necessary control and I/O circuitry
to
provide
~~fi~~"'~\';ra~f'~t{sM'.'f~~uirem~ts
of dynamic
RAMs.
The chip's
high
performance makes it especially suitable for use with
hi9Q{(-'-~>~~":;;~~~b_,~~J;~RAIYl~1ike
the
81078.
The 8222
is
designed
for
large, asynchronously driven, dynamic memory systems.
~~';;~~;~'~"!J;F~j»)
eft
5-99