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SILICON GATE MOS 8702A
PROGRAMMING OPERATION
D.C. AND OPERATING CHARACTERISTICS FOR PROGRAMMING OPERATION
T
A
= 25°C, Vee =
OV,
V
ss
= +12V ± 10%,
CS
=
OV
unless otherwise noted
SYMBOL TEST
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I
Ll1
P
Address and Data Input 10
rnA
V
IN
=
-48V
Load Current
'LI2P
Program and VG G 10
rnA
V
IN
=
-48V
Load Current
'ss
V
ss
Supply Load Current
.05 rnA
IOOp(l)
Peak 1
00
Supply
200
mA
V
oo
= V
pro,7
-48V
Load Current
V
GG
=
-35
V
IHP
Input High Voltage
0.3
V
V
IL1P
Pulsed Data
Input
-46
-48
V
Low Voltage
V
1L2P
Address I
nput
Low
-40
-48
V
Voltage
V
IL3P
Pulsed Input Low V
oo
-46
-48
V
and Program Voltage
V
IL4P
Pulsed I
nput
Low
-35
-40
V
V
GG
Voltage
Note
1:
lOOp
flows
only
during
VOO,
VGG
on
time.
lOOp
should
not
be
allowed
to
exceed
300mA
for
greater
than
100~sec.
Average
power
supply
current
lOOp
is
typically
40
mA
at
20%
duty
cycle.
A.C. CHARACTERISTICS FOR PROGRAMMING OPERATION
TAMSIENT
=
25°C,
Vee =
OV,
V
ss
= + 12V ± 10%,
CS
=
OV
unless otherwise noted
SYMBOL
TEST
MIN.
TYP. MAX.
UNIT
CONDITIONS
Duty Cycle
(V
oo
, V
GG
)
20
%
t~pw
Program Pulse Width
3
ms
VG
G
=
-35V,
V
oo
=
V
prog
=
-48V
tow
Data
Set
Up Time
25
IlS
tOH
Data Hold Time
10
IlS
tvw
V
oo
, V
GG
Set
Up
100
IlS
tvo
V
oo
, V
GG
Hold
10
100
J.1S
tACW
(2)
Address Complement
25
IlS
Set Up
tACH
(2)
Address Complement 25
J.1S
Hold
tATW
Address True
Set
Up
10
J.1S
tATH
Address True Hold
10
J.1S
Note
2.
All
8
address
bits
must
be
in
the
complement
state
when
pulsed
Vee
and
VGG
move
to
their
negative
levels.
The
addresses
(0
through
255)
must
be
programmed
as
shown
in
the
timing
diagram
for
a
minimum
of
32
times.
5-41