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SCHOTTKY BIPOLAR 8228
FUNCTIONAL DESCRIPTION
General
The
8228
is a single
chip
System
Controller
and
Data Bus
driver
for
the
8080
Microcomputer
System.
It generates all
control
signals required
to
directly interface
MCS-80™
family
RAM, ROM,
and
I/O
components.
Schottky
Bipolar
technology
is
used
to
maintain
low delay
times
and provide high
output
drive
capability
to
support
small
to
medium
systems.
Bi-Directional
Bus
Driver
An eight bit, bi-directional
bus
driver
is
provided
to
buffer
the
8080
data
bus
from Memory
and
I/O devices.
The
8080A
data
bus
has an
input
requirement
of
3.3
volts (min)
and
can
drive (sink) a
maximum
current
of
1.9mA.
The
8228
data
bus
driver assures
that
these
input
requirements will
be
not
only
met
but
exceeded
for
enhanced
noise immunity.
Also,
on
the
system side
of
the
driver
adequate
drive cur-
rent
is
available
(10mA
Typ.) so
that
a large
number
of
Memory
and
I/O devices
can
be
directly
connected
to
the
bus.
The
Bi-Directional Bus Driver is
controlled
by
signal~
from
the
Gating Array
so
that
proper
bus
flow
is
maintained and
its
outputs
can
be
forced
into
their
high impedance
state
(3-state)
for
DMA activities.
Status Latch
At
the
beginning
of
each machinecycle
the
8080
CPU issues
"status"
information
on
its
data
bus
that
indicates
the
type
of
activity
that
will
occur
during
the
cycle.
The
8228
stores
this information in
the
Status
Latch
when
the
STSTB
input
goes
"low".
The
output
of
the
Status
Latch
is
connected
to
the
Gating Array
and
is
part
of
the
Control Signal generation.
Gating Array
The
Gating
Array
generates
control
signals
(MEM
R,
MEM
W,
I/O R, I/O
Wand
INTA)
by
gating
the
outputs
of
the
Status
Latch
with
signals
from
the
8080
CPU (DBIN, WR,
and
HLDA).
The
"read"
control
signals (MEM R, I/O
Rand
INTA) are
derived from
the
logical
combination
of
the
appropriate
Status
Bit
(or
bits)
and
the
DBIN
input
from
the
8080
CPU.
The
"write"
control
signals (MEM
W,
I/O
W)
are derived
from
the
logical
combination
of
the
appropriate
Status
Bit
(or bits) and
the
WR
input
from
the
8080
CPU.
All Control Signals are
"active
low"
and
directly
interface
to
MCS-80 family RAM,
ROM
and
I/O
components.
The
INTA
control
signal
is
normally used
to
gate
the
"inter-
rupt
instruction
port"
onto
the
bus. It also provides a
special
feature
in
the
8228.
If
only
one
basic
vector
is
need-
ed in
the
interrupt
structure,
such as in small systems,
the
8228
can
automatically
insert a RST 7
instruction
onto
the
bus
at
the
proper
time.
To
use
this
option,
simply
connect
the
INTA
output
of
the
8228
(pin 23)
to
the
+12
volt
supply
through
a series resistor
(1
K ohms).
The
voltage
is
sensed internally
by
the
8228
and logic
is
"set-up"
so
that
when
the
DBIN
input
is
active a RST 7
instruction
is
gated
on
to
the
bus
when
an
interrupt
is
acknowledged. This
feature provides a single
interrupt
vector
with
no
additional
components,
such as an
interrupt
instruction
port.
When using
CALL
as
an
Interrupt
instruction
the
8228
will generate
an
INTA pulse
for
each
of
the
three
bytes.
The
BUSEN (Bus Enable)
input
to
the
Gating
Array
is
an
asynchronous
input
that
forces
the
data
bus
output
buffers
and
control
signal buffers
into
their
high-impedance
state
if it
is
a
"one".
If BUSEN
is
a
"zero"
normal
operation
of
the
data
buffer
and
control
signals
take
place.
SYSTEM
DATA
BUS
CPU
DATA
BUS
8228 BLOCK DIAGRAM
BI-OIRECTIONAL
BUS
DRIVER
DRIVER CONTROL
STSTB
----.
--J
DBIN
----.-------------41
WR
--.-------------011
HLDA
----.--------------1
5-8
GATING
ARRAY