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SILICON GATE MOS
81078·4
Read
Modify
Write
Cycle£1]
Symbol
Parameter
Min.
Max.
Unit
Conditions
t
RWC
Read
Modify
Write(
RMW)
590
ns
tT
=
20ns
Cycle
Time
t
CRW
CE
Width
During
RMW
420
3000
ns
WC
WE
to
CE
on
0
ns
t
w
WE
to
CE
off
150
ns
C
load
=
50pF,
Load
=
One
TTL
Gate,
twp
WE
Pulse
Width
50
ns
Ref
=
2.0V
tow
DIN
to
WE
Set
Up
0
ns
t
OH
DIN
Hold
Time
0
ns
tco
CE
to
Output
Delay
250
ns
t
ACC
Access
Time
270
ns
tACC
=
tAC
+
tco
+
ltT
(Numbers in parentheses
are
for
minimum cycle
timing
in
ns.)
WE
CAN
CHANGE
ADDRESS CAN CHANGE ®
1..-------t
w
(150)
---------1
ADDRESS STABLE
®
.--tAC(O)
~---tAH(50)----.f
~-------------
t
CRW
(420)
---------------~
14-------------------
t
RWc
(590)
CD-----------------
.....
I
"'H
-------lI-P
......
------------
......
1
V
IHC
----j---i-II------------------------------..l
CE
'leH
ADDRESSES
ANDes
~l
--.
.-tow(O)
DIN CAN
CHANGE
HIGH
IMPEDANCE
tCF(O)
DtN
STABLE
-----VALlD--------.1
~-----------------I--
-
--
---
--
VOH----
-
..---t
cO
(250)
-----.1
V
il
----+-
.....
----------~
DIN CAN CHANGE
V
IH
----+-
.....
----------~
D-O-U-T
IMP~~G:NCE
VOl----!:.._
~
__
~
t
Acc
(270)
-----.1
NOTES:
1.
A.C.
characteristics
are guaranteed
only
if
cumulative
CE
on
time
during
tREF
is
~65%
of
tR
EF.
For
continuous
Read-Modify-Write
operation,
tcc
and
tRWC
should
be
increased
to
at
least
185ns
and
645ns,
respectively.
2.
V'L
MAX
is
the reference level
for
measuring
timing
of
the
aadresses,
CS,
WE, and
DIN·
3.
VI
H
MIN
is
the reference level
for
measuring
timing
of
the
addresses,
CS,
WE, and
DIN·
4.
VSS
+2.QV
is
the reference level
for
measuring
timing
of
CEo
5.
VOO
-2V
is
the
reference level
for
measuring
timing
of
CEo
6. VSS +2.QV
is
the reference level
for
measuring the
timing
of
DOUT'
7. WE
must
be
at
VIH
until
end
of
tco.
8.
During
CE
high
typically
a.5mA
will
be
drawn
from
any
address
pin
which
is
switched
from
low
to
high.
5-88