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Silicon Gate MOS 8102-2
• Simple Memory Expansion - Chip
Enable Input
• Fully Decoded - On Chip Address
Decode
• Inputs Protected - All Inputs Have
Protection Against Static Charge
• Low Cost Packaging
-16
Pin Plastic
Dual-In-Line Configuration
1024
BIT FULLY DECODED STATIC MOS
RANDOM ACCESS MEMORY
• Access Time - 850ns Max.
• Single +5 Volts Supply Voltage
• Directly TTL Compatible - All Inputs
and Output
• Static MOS - No Clocks
or
Refreshing Required
• Low Power - Typically 150
mW
• Three-State Output - OR-Tie
Capability
The Intel@8102-2
is
a 1024
word
by
one
bit
static random
access
memory
element using
normally
off
N-channel MOS devices integrated on a
monolithic
array.
It
uses
fully
DC
stable (static)
circuitry
and
therefore requires no clocks
or
refreshing
to
operate. The data
is
read
out
nondestructively and
has
the
same
polarity
as
the
input
data.
The
8102-2
is
designed
for
microcomputer memory applications where high performance, low cost, large
bit
storage,
and
simple interfacing
are
important
design objectives.
It
is
directly
TTL
compatible in all respects: inputs,
output,
and a single +5
volt
supply. A separate chip
enable (CE)
lead
allows
easy
selection
of
an
individual package when
outputs
are
OR-tied.
The Intel®8102-2
is
fabricated
with
N-channel silicon gate technology. This technology allows the design
and
production
of
high performance, easy-to-use MOS circuits and provides a higher
functional
density on
a
monolithic
chip than either conventional MOS technology
or
P-channel silicon gate technology.
Intel's silicon gate technology also provides excellent protection against contamrnation. This permits the
use
of
low
cost silicone packaging.
BLOCK
DIAGRAM
PIN CONFIGURATION
LOGIC SYMBOL
A
6
16
A
7
As
2
15
As
A
o
A,
RIW
3
14
A
g
A
2
DIN
A
J
A,
4
13
CE
A
4
8102-2
As
8102-2
A
2
5
12
DATA
OUT
A
6
A
J
6
11
DATA
IN
A
7
As
DOUT
A
4
7
10
Vee
A
g
Ao
8
9
GND
CE
R/W
PIN NAMES
DIN
DATA
INPUT
CE
CHIP ENABLE
Ao- Ag
ADDRESS INPUTS
DOUT
OATA OUTPUT
RIW
READIWRITE INPUT
Vee
POWER
(+5V)
R/W
DATA
IN
0= PIN NUMBERS
5-75
CELL
ARRAY
32
ROWS
32 COLUMNS
COLUMN I/OCIRCUITS
DATA
OUT