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Silicon Gate MOS
8257
PROGRAMMABLE DMA CONTROLLER
ORO 3
oACK
2
OACK 3
ORO 2
OACK
1
OACK 0
+--
ORO 1
cl}mputer systems. Its pri-
allow the peripheral
to
ac-
;the system bus. It
also
keeps
"grar11mable
terminal
count
has
~<,
amon9,$fl'e
four
channels, program-
for
s~~tbred
data transfers,
an
auto-
/'dur!~:~i)DMA
cycles. There
are
three
PRIORITY
RESOLVER
e ¢2,.JJTL) clock
of
the
8080
system.
It
is
'"Mulff;J3I'e
DMA
chips
can
be
used
to
expand
~
..
,.::-,/
c~::~"t
• Auto Load Mode
• Single TTL Clock
«(/)21
TTL)
• Single
+5V
SUR~~
~~:W~l~\:~~
'.'.,
• Expandable
•
40
Pin
Du
A
4
----1
As
----1
A
6
----1
A
7
----1
CONTROL
HOLD
..........
---1
LOGIC
HLDA----..
MEMR
---ClIII
MEMW
----<...JI
AEN
----1
AoSTB
----1
cs-----
REAoY----.tI
• Four Channel DMA Controller
• Priority DMA Request Logic
• Channel Inhibit Logic
• Terminal and Modulo
256/128
Outputs
The 8257
is
a
Direct
Memory
Access
(DMA)
Chip which
has
four
channels
for
use
i
mary
function
is
to
generate, upon a peripheral request, a sequential memory a
ress
cess
or
deposit data
directly
from
or
to
memory.
It
uses
the Hold feature
of
th
count
of
the number
of
DMA
cycles
for
each
channel and notifies the periphe
been
reached. Other features
that
it
has
are
two
mode
priority
logic
to
res/
mabie channel
inhibit
logic,
an
early
write
pulse
option,
a modulo 256/1
matic load mode, a terminal
count
status register, and control
signaL;:-·
.
types
of
DMA
cycles:
Read
DMA
Cycle,
Write
DMA
Cycle and Verify,/,t
The 8257
is
a 40-pin, N-channel MOS chip which
uses
a single
~;
designed
to
work
in
conjunction
with
a single 8212 8-bit,
thr~
the number
of
channels
with
the aid
of
the
8214
Priority
Inter'
TC
..........
----'"
128/256
..----------'
INTERNAL
BUS
5-171