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Silicon Gate MOS
8259
PROGRAMMABLE INTERRUPT CONTROLLER
r up
to
64
vectored
priority
technology and requires a
IR 0
4---IR
1
REQUEST
IR
2
LATCH
4---
IR 3 INTERRUPT
MASK
.--
IR 4 REQUESTS
REGISTER
4---
IR 5
"'-IR6
"'-IR7
READ!
WRITE
LOGIC
• Individual Request Mask
Capability
• Single
+5V Sup
(No Clocks)
• 28 Pin Dua ckage
o
CS-------It
CASO~--.nI
CAS1 ....
--....n
CAS 2
"""---.nII
SP
~--.nII
CONTROL
LOGIC
PIN CONFIGURATION
• Eight Level Priority Controller
• Expandable
to
64
Levels
• Programmable Interrupt
Modes (Algorithms)
The 8259 handles
up
to
eight vectored
priority
interrupts
for
the
8080A
CPU. I
interrupts,
without
additional
circuitry.
It
will
be,
packaged in a 28-pin
plasf
single
+5V
supply.
Circuitry
is
static, requiring no clock input.
The 8259
is
designed
to
minimize
the software and
real
time overhead in
modes,
permitting
optimization
for
a variety
of
system requirements.
INT......----I
INTA---.nI
~INTERNALBUS
5-173