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RAM
memory
must
be
provided,
such
as:
Floppy
Disk,
Paper Tape,
etc.
The CPU
treats
RAM
in
exactly
the
same
manner
as
ROM
for addressing
data
to
be
read.
Writing
data
is
very
similar;
the
RAM
is
issued
an
address
during
the
first por-
tion
of
the
Memory Write cycle (T1 &
T2)
in
T3
when
the
data
that
is
to
be
written
is
output
by
the
CPU
and
is
stable
on
the
bus an MEMW
command
is
generated.
The
MEMW
signal
is
connected
to
the
R/W
input
of
the
RAM
and
strobes
the
data
into
the
addressed
location.
In
Figure 3-7 a typical Memory
system
is
illustrated
to
show
how
standard
semiconductor
components
interface
to
the
8080
bus.
The
memory
array
shown
has
8K
bytes
• ®
(8
bits/byte)
of
ROM
storage,
uSing
four
Intel
8216As
and
512
bytes
of
RAM
storage,
using Intel
8111
static
RAMs.
The
basic interface
to
the
bus
structure
detailed
here
is
common
to
almost
any
size
memory.
The
only
ad-
dition
that
might
have
to
be
made
for
larger systems
is
more buffers
(8216/8212)
and
decoders
(8205)
for
gener-
ating
"chip
selects."
The
memories
chosen
for
this
example
have an access
time
of
850
nS (max)
to
illustrate
that
slower, economical
devices
can
be
easily interfaced
to
the
8080
with
little ef-
fect
on
performance.
When
the
8080
is
operated
from
a
clock
generator
with
a
tCY
of
500
nS
the
required
memory
access
time
is
Approx.
450-550
nS. See
detailed
timing
specification Pg.
5-16.
Using
memory
devices
of
this
speed
such as Intel@8308,
8102A,
8107A,
etc.
the
READY
input
to
the·
8080
CPU
can
remain
"high"
because
no
"wait"
states are required.
Note
that
the
bus
interface
to
memory
shown in Figure 3-7 remains
the
same. However, if slower
memories
are
to
be
used, such as
the
devices illustrated
(8316A,
8111)
that
have access
times
slower
than
the
min-
imum
requirement
a simple logic
control
of
the
READY
input
to
the
8080
CPU will insert
an
extra
"wait
state"
that
is
equal
to
one
or
more
clock
periods
as
an
access
time
"adjustment"
deiay
to
compensate.
The
effect
of
the
extra
"wait"
state
is
naturally
a slower
execution
time
for
the
instruction.
A single
"wait"
changes
the
basic
instruction
cycle
to
2.5
microSeconds.
8K
+ 512
RAM
8K
o
ROM
MEMORY
MAP
ROM
RAM
-----------,
----------
....
#4.:.- ...........
#3;;.
..-.
#2
#1
8111
FiJW
00
1/0 1-4 AO-A7
8111
R/W
00
1/01-4 AO-A7
AO-A7
8316A
01-08
CS3
CS2
AO-Al0
All-
A12
_01.--_0
DATA
BUS
IsiJL.-..--_IJL--.------L----_DL----
CONTROL
BUS (6)
_-.-ill
n
11_
ADDRESS BUS (16)
Figure 3-7. Typical
Memory
Interface
3-7