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OSCILLATOR
CLOCK GENERATOR
7486
DB
OB
74163
DC
OC
.......--...-------'
74S04
~
20MHz
330
330
~""""--01
>-
......
------------
.......
--------
....
OSC
7486
READY
r-----IIIIII----
SYNC
AUXILIARY
FUNCTIONS
WA
IT
REO
------41---1
0 a
74574
ClK
'----........--410
74S74
ClK
0.......-..-.-----..
tf>1A
(TTL)
74HOO
10--+---------
..
4>2
(TTL)
WAVEFORMS
GND--+-~
4>1
----u
u
---f
1~~~
~50ns
4>2
--'
\ 250ns ,
'~
__
-Ir-
50ns~
t+-
--.f
r-
50ns
4>1A
---I , 250ns , , I
SYNC
---1'
,\,.-_---1'
\
DMAREO--~----IID
a
74S74
ClK
HOLD
Figure 3-3. 8080 Clock Generator
20
MHZ oscillator, a
four
bit
counter,
and
gating
circuits.
The
oscillator provides a
20
MHZ signal
to
the
input
of
a four (4)
bit,
presettable,
synchronous,
binary
counter.
By
presetting
the
counter
as shown
in
figure
3-3
and clocking it with
the
20
MHZ signal, a simple
decoding
of
the
counters
outputs
using
standard
TTL
gates, provides
proper
timing
for
the
two
(2)
8080
clock inputs.
Note
that
the
timing
must
actually be measured
at
the
output
of
the
High Level Driver
to
take
into
ac-
count
the
added delays
and
waveform
distortions
within such a device.
positive
transition
when
biased
from
the
8080
Voo
supply
(12V)
but
to
achieve
the
low voltage specifi-
cation
(V
ILC
)
.8 volts Max.
the
driver
is
biased
to
the
8080 V
ss
supply
(-5V). This allows
the
driver
to
swing from GND
to
Vo
o
with
the
aid
of
a simple
resistor divider.
A low resistance series
network
is
added
between
the
driver
and
the
8080
to
eliminate
any
overshoot
of
the
pulsed waveforms. Now a
circuit
is
apparent
that
can
easily
comply
with
the
8080 specifications. In
fact
rise
and
falltimes
of
this
design are typically less
than
10 ns.
Figure 3-4. High Level Driver
100n
-5V
.68
J.LF
+12V
6
6S0pF
47n
cf>1
cf>1
(TTL)
---1
2
MH0026
(SOSO
PIN 22)
680
pF
OR
¢2
(TTL)-)
4
EQUIV.
5
47n
¢2
(8080
PIN 15)
3
15K
15K
High Level Driver Design
The
voltage level
of
the
clocks
for
the
8080
is
not
TTL
compatible
like
the
other
signals
that
input
to
the
8080.
The
voltage swing
is
from
.6 volts (V
ILC
)
to
11
volts
(V
IHC
)
with
risetimes
and
falltimes
under
50 ns.
The
Capacitive Drive
is
20
pf
(max.).
Thus,
a
High Level Driver
is
required
to
interface
the
outputs
of
the
Clock
Generator
(TTL)
to
the
8080.
The
two
(2)
outputs
of
the
Clock
Generator
are ca-
pacitivity
coupled
to
a dual- High Level clock driver.
The
driver
must
be
capable
of
complying
with
the
8080 clock
input
specifications, page 5-15. A driver
of
this
type
usually has little
problem
supplying
the
3-3