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INTA*
STACK
°2
HLTA
°3
OUT
°4
M,
°5
INP*
°6
MEMR*
0
7
Instructions
for
the
8080
require from
one
to
five machine
cycles
for
complete
execution.
The
8080
sends
out
8
bit
of
status
informatton
on
the
data
bus
at
the
beginning
of
each
machine
cycle
(during SYNC
time).
The
following
table
defines
the
status
information.
STATUS
INFORMATION
DEFINITION
Data
Bus
Bit Definition
00
Acknowledge signal
for
INTERRUPT
re-
quest. Signal
should
be used
to
gate a
re-
start
instruction
onto
the
data
bus
when
OBIN
is
active.
0,
Indicates
that
the
operation
in
the
current
machine cycle will be a
WR
ITE
memory
or
OUTPUT
function
(WO
= O).Otherwise,
a REAO
memory
or
INPUT
operation
will
be
executed.
Indicates
that
the
address bus holds
the
pushdown
stack address from
the
Stack
Pointer.
Acknowledgesignal
for
HALT instruction.
Indicates
that
the
address bus
contains
the
address
of
an
output
device and
the
data
bus
will
contain
the
output
data
when
WR
is
active.
Provides a signal
to
indicate
that
the
CPU
is
in
the
fetch
cycle
for
the
first
byte
of
an
instruction.
Indicates
that
the
address bus
contains
the
address
of
an
input
device
and
the
input
data
shou
Id
be placed
on
the
data
bus
when
OB
IN
is
active.
Designates
that
the
data
bus will be used
for
memory
read
data.
*These three status bits can be used
to
control
the
flow of
data
onto
the
8080
data bus.
STATUS WORD CHART
DO
INTA
02
STACK
03
HLTA
04
OUT
06
INP
07 MEMR
Table 2-1.
8080
Status Bit Definitions
2-6
8080
STATUS
LATCH
o
10
o 9
0,
o 8
2 7
0
3
3
8080
0
4
4
0
5
5
~6
6
7
SYNC
19
-
OBIN
~
01
02
STATUS
22
15
LATCH
--2.
0
1
DO
~
5
~
~
~
9
~
16
.lL.
18
8212
17
20
JL
--
22
~
CLOCK GEN.
(olTTl)
&
DRIVER
~
r;;
CLR
OS2
MO
OS,
13 12
Y1
I I
~
T2
01
SYNC
OATA
1------
''---t--t--
STATUS
......-.----+001'----1
TYPE OF
MACHINE
CYCLE
I
INTA
W6
STACK
HlTA
OUT
M1
INP
MEMR
DBIN