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SILICON GATE
MOS
M8080A
A.C. CHARACTERISTICS (Continued)
T
A
=
-55°C
to
+125°C,
VOO
=
+12V
±10%, Vee =
+5V
±10%,
VBB
=
-5V
±10%,
Vss
=OV, Unless Otherwise Noted.
Symbol
Parameter
Min. Max.
Unit
Test
Condition
tOS2
Data Setup
Time
to
¢2
During
DBIN
130
nsee
tOH
[1]
Data
Hold
Time
From
¢2
During
DBIN
50
nsee
tiE
(2)
INTE
Output
Delay From ¢2
200
nsee
C
L
=
50pf
tRS
READY
Setup
Time
During
¢2
120
nsee
tHS
HOLD
Setup
Time
to
¢2
140
nsee
tiS
I
NT
Setup
Time
During
¢2 (During
4>1
in
Halt
Mode)
120 nsee
tH
Hold
Time
From
¢2 (READY,
INT,
HOLD)
0 nsee
tFD
Delay
to
Float
During Hold
(Address
and
Data
Bus)
130
nsee
tAW [2]
Address Stable Prior
to
WR
-
[5]
nsee
tDW[2]
Output
Data Stable
Prior
to
WR
[6]
nsee
tWD[2]
Output
Data Stable
From
WR
[7]
nsee
tWA
[2]
Address Stable From
WR
[7]
nsee
~
C
L
=50pf
tHF[2]
H
LOA
to
Float
Delay
[8]
nsee
tWF[2]
WR
to
Float
Delay
[9]
nsee
tAH [2]
Address
Hold
Time
After
DBIN
During
HLDA
-20
nsee
-
NOTES:
1.
Data
input
should
be
enabled
with
OBIN
status.
No
bus
conflict
can then occur and data
hold
time
is
assured.
tOH
=
50
ns
or
tOF,
whichever
is
less.
2.
Load Circuit.
+5V
8080A
OUTPUT
3.
tey
=
t03
+ t
r
q,2
+
tq,2
+ tfq,2 +
tD2
+ t
r
q,l
~
480ns.
+100
+50
~
CAPACITANCE
(pf)
(CACTUAL
- C
SPEC
)
o
-50
oS
>
+10
«
..J
w
0
....
0
:::J
Q.
....
:::J
-10
0
-1
-20
-100
TYPICAL
~
OUTPUT
DELAY
VS.
~
CAPACITANCE
+20
r-----~---~---_---_
..........
~---
.......
-----
.....
---
DBIN
SYNC
READY
WAIT
HOLD fa-
HLDA
INT
INTE
~
t
oe
'-
4. The
following
are relevant when interfacing
the
M8080A
to
devices having VIH =
3.3V:
a)
Maximum
output
r'ise
time
from
.8V
to
3.3V
= lOOns @
CL
=SPEC.
b)
Output
delay
when
measured
to
3.0V
=SPEC +60n5 @
CL
=SPEC.
d
If
CL
*SPEC, add
.6ns/pF
if
CL>
CSPEC,
subtract
.3n5/pF
(from
modified
delay)
if
CL
< CSPEC.
5.
tAW
= 2
tey
-t03
-t
r
ct>2
-140nsec.
6.
tow
=
tCY
-t03
-t
r
ep2
-170nsec.
7.
If
not
HLOA,
two
=
tWA
=
t03
+ t
r
¢2
+10ns.
If
HLOA,
two
=
tWA
= tWF·
8. tHF
=
t03
+ t
r
q,2
-50ns.
9.
tWF
=
tD3
+ t
r
<t>2
-10ns
10. Data
in
must
be stable
for
this
period
during
DBIN
·T3.
Both
tOS1 and tOS2
must
be
satisfied.
11. Ready signal
must
be stable
for
this
perio~
during
T2
or
TW.
(Must
be
externally
synchronized.)
12.
Hold
signal
must
be stable
for
this
period
during
T2
or
TW
when
entering
hold
mode,
and
during
T3, T4, T5
and
TWH
when
in
hold
mode.
(External
synchronization
is
not
required.~
13.
Interrupt
signal
must
be stable
during
this
period
of
the
last
clock
cycle
of
any
instruction
in order
to
be
recognized
on
the
following
instruction.
(External
synchronization
is
not
required.)
14.
This
timing
diagram shows
timing
relationships
only;
it
does
not
represent
any
specific
machine
cycle.
5-34