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SILICON GATE MOS 8257
8257 PRELIMINARY FUNCTIONAL DESCRIPTION
The
transfer
of
data
between
a mass storage device such as
a
floppy
disk
or
mag cassette
and
system
RAM
memory
is
often
limited
by
the
speed
of
the
microprocessor. Removing
the
processor
during
such a
transfer
and
letting
an
auxiliary
device manage
the
transfer
in
a
more
efficient manner would
greatly improve
the
speed
and
make
mass storage devices
more attractive, even
to
the
small
system
designer.
The
transfer
technique
is
called DMA (Direct Memory Ac-
cess); in essence
the
CPU
is
idled so
that
it
no
longer has
control
of
the
system
bus
and
a DMA
controller
takes
over
to
manage
the
transfer.
The
8257
Programmable DMA Controller
is
a single chip,
four channel device
that
can efficiently manage DMA activ-
ities. Each channel
is
assigned a
priority
level so
that
if
multi-DMA activities are required
each
mass storage device
can be serviced, based
on
its
importance
in
the
system. In
operation,
a
request
is
made
from
a peripheraI device
for
access
to
the
system
bus.
After
its priority
is
accepted
a
HOLD
command
is
ussued
to
the
CPU,
the
CPU issues
a HLDA
and
that
DMA channel has
complete
control
of
the
system bus. Transfers can
be
made in blocks, suspending
the
processors
operation
during
the
entire
transfer
or,
the
transfer can
be
made a
few
bytes
at
a
time,
hidden
in
the
execution
states
of
each
instruction
cycle, (cycle-stealing).
The
modes
and
priority
resolving are maintained
by
the
system
software
as well as initializing
each
channel as
to
the
starting address
and
length
of
transfer.
The
system interface
is
si
mi
lar
to
the
other
periphera
Is
of
the
MCS-80
but
an additional
8212
is necessary
to
control
the
entire
address bus. A special
control
signal BUSEN
is
connected
directly
to
the
8228
so
that
the
data
bus
and
control
bus
will be released
at
the
proper
time.
ADDRESS BUS
\
ADDRESS BUS (16)
\
~
CONTROL BUS
\
flOW
ilOR
HOLD
RESET
~
DATA
BUS (8)
\
A
s
-A,5
4:/'\~
MEMR
MEMW
READY
1/
V
8
/ A
o
-A
3
/
A
4
-A
7
'---
l/L--
8
8212
['r-
92(TTL)
t
t
HLDA
BUSEN
8228
I 1
"',/7
CS
A
o
·A
3
A
4
-A
7
AOSTB
AEN
0
7
-0
0
I/O
MEM
HOLD
HLOA
CLK
ROYIN
RESET
W
R
if
W
8257
128/256
DACK ORO
DACK ORO
DACK
ORO
DACK
ORO
MOD
TC
3
3
2 2 1 1
0
0
~
!
~
t
l
t
l
1
l
f
I
OMA CHANNEL REOUESTS
AND
ACKNOWLEDGES
System Interface 8257.
8257
AND
8212
ORO 0
......-----11
DACK 0
1------..
ORO
11..-----1
DACK
1
I___-----.t
ORO 2
......
----11
DACK 21------...
ORO 3
1+------1
DACK
31--------..
DISK 1
DISK 2
SYSTEM
RAM
MEMORY
OMA CONTROLLER
System
Application
of
8257.
DUAL
FLOPPYDISK CONTROLLER
5-172