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CHAPTER 4 I/O PORTS
4.7.2 Operations of Port 7 Functions
This section describes the operation of port 7.
■ Operation of Port 7
● Operation in output port mode
When "1" is written for a bit of the DDR7 register, the bit corresponding to a pin of port 7, the pin
functions as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the
pin.
Once data has been written into the PDR7 register, the written data is held in the output latch and output
to the pin as it is.
The value state of the pin can be read by reading the PDR7 register.
● Operation in input port mode
When "0" is written for a bit of the DDR7 register, the bit corresponding to a pin of port 7, the pin
functions as an input port.
In input port mode, the output transistor is OFF and the pin status is Hi-Z.
Once data has been written into the PDR7 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR7 register.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR7 register are initialized to "0". Thus, all output transistors
become OFF and the pins become Hi-Z.
However, CPU resets do not initialize the PDR7 register. If a pin is used as an output port after the
reset, reinitialize the PDR7 register to contain new output data in the bit position corresponding to the
pin and then set the corresponding bit of the DDR7 register so that the pin will function as an output
port.
● Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is "1" and when the stop
mode is entered, the output transistor is turned OFF and the pin becomes Hi-Z because the output
transistor is forcibly turned OFF without respect to the value existing on the DDR7 register in the bit
position corresponding to the pin.
Input remains fixed to prevent leaks by input open.