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CHAPTER 6 WATCHDOG TIMER
6.4 Operations of Watchdog Timer Functions
The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
■ Operations of Watchdog Timer
● Activating watchdog timer
The watchdog timer is activated when the first time "0101
B
" is written to the watchdog control bits
(WDTC: WTE3 to WTE0) of the watchdog control register.
The watchdog timer cannot be stopped without accepting a reset upon activation.
● Clearing watchdog timer
The watchdog timer counter is cleared the second or subsequent time "0101
B
" is written to the watchdog
control bits (WDTC: WTE3 to WTE0) of the watchdog control register.
When the counter is not cleared within the time interval of the watchdog timer, the counter overflows and
the timer generates the internal reset signal having a period of four instruction cycles.
● Time intervals of watchdog timer
The time interval varies depending on the timing at which the watchdog timer is cleared. Figure 6.4-1
shows the relationship between the clear timings and time intervals of the watchdog timer when output
from the time-base timer is used as the count clock (oscillation frequency: 12.5 MHz).
Figure 6.4-1 Clearing Watchdog Timer and Time Interval
671.0 ms
335.5 ms
Minimum time interval
Count clock output from
time-base timer
Watchdog clear
Overflow
Watchdog 1-bit counter
Watchdog reset
Maximum time interval
Count clock output from
time-base timer
Watchdog clear
Overflow
Watchdog 1-bit counter
Watchdog reset