Fujitsu MB89202 Computer Hardware User Manual


 
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CHAPTER 12 A/D CONVERTER
Clock selector
The clock selector selects the clock to be used to activate A/D conversion while continuous activation is
enabled (ADC2: EXT = 1).
Analog channel selector
This circuit selects one out of the eight analog inputs.
Sample hold circuit
This circuit holds the input voltage selected by the analog channel selector. By performing the sample hold
of the voltage input immediately after the activation of A/D conversion, A/D conversion can be performed
without the variance of the input voltage affecting it during A/D conversion (during comparison).
D/A converter
This generates the voltage that corresponds to the values set in the ADDH and ADDL registers.
Comparator
This compares the input voltage for which sample hold is performed, with the output voltage of the D/A
converter to determine which is the greater of the two.
Control circuit
The control circuit has the following function.
For A/D conversion functions, this circuit determines the values in turn from the MSB in the 10-bit A/D
data register toward the LSB based on the large and small signals from the comparator. When the
conversion is completed, it sets the interrupt request flag bit (ADC1: ADI).
A/D data register (ADDH and ADDL)
The high-order 2 bits of 10-bit A/D data are stored in the ADDH register. The low-order 8 bits of 10-bit
A/D data are stored in the ADDL register.
The ADDH and ADDL registers have the following function.
For A/D conversion function, these registers store the results of A/D conversion.
A/D control register 1 (ADC1)
This register is used to enable and disable functions, select an analog input, check statuses, and control
interrupts.
A/D control register 2 (ADC2)
This register is used to select an input clock, enable and disable interrupts, select functions, and perform
other activities.
Interrupts of the A/D converter
When the set conditions are satisfied at the completion of A/D conversion for IRQ8, if an interrupt request
output is enabled (ADC2: ADIE = 1), an interrupt request occurs.