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CHAPTER 3 CPU
● Transition to and cancellation of clock mode (non-standby mode)
● Transition to and cancellation of standby mode
Note:
In standby mode, the CPU and watchdog timer stop. Thus, software and watchdog resets do not occur.
Table 3.7-3 Transition to and Cancellation of Clock Mode
State transition Transition conditions
Transition to active mode after
power-on reset
(9) End of oscillation stabilization wait time (output of time-base timer)
(1) Cancellation of reset input
Reset in RUN mode (2) External reset, software reset, or watchdog reset
Table 3.7-4 Transition to and Cancellation of Standby Mode
State transition Transition conditions
Transition to sleep mode (3) STBC: SLP=1
Cancellation of sleep mode
(6) Interrupt (each type)
(4) External reset
Transition to stop mode (5) STBC: STP=1
Cancellation of stop mode
(7) External interrupt
(8) End of oscillation stabilization wait time (output of the time-base timer)
(10) External reset
(11) External reset (during oscillation stabilization wait)