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CHAPTER 3 CPU
3.7.2 Sleep Mode
This section describes sleep mode.
■ Operations Relating to Sleep Mode
● Transition to sleep mode
In sleep mode, the operating clock for CPU is stopped. Although the CPU stops storing data in the registers
and RAM used immediately before transition to sleep mode, peripheral functions, excepting the watchdog
timer, continue to operate.
Writing "1" to the sleep bit in the standby control register (STBC: SLP) results in a transition to sleep
mode. Any attempt to write "1" into the SLP bit while an interrupt request is being generated fails,
transition to sleep mode cannot be made, and instructions are processed continuously. (Even after the
interrupt is processed completely, transition to sleep mode is not possible.)
● Cancellation of sleep mode
Sleep mode is cancelled by a reset or interrupt from a peripheral function.
Pin states are initialized by the reset operation.
When an interrupt request with an interrupt level higher than 11
B
is generated in a peripheral function or
external interrupt circuit in sleep mode, sleep mode is cancelled regardless of the CPU interrupt enable flag
(CCR: I) or interrupt level bits (CCR: IL1 and IL0).
When sleep mode is cancelled, a normal interrupt operation is performed, and if interrupts are acceptable,
interrupt processing is performed. Otherwise, if interrupts are unacceptable, the processing resumes starting
from an instruction next to the instruction which was issued immediately before transition to sleep mode.