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CHAPTER 9 12-BIT PPG TIMER
9.6 Notes on Using 12-bit PPG Timer
This section provides notes on using the 12-bit PPG timer.
■ Notes on Using 12-bit PPG Timer
● Output pin changeover
The P37/BZ/PPG pin shares functions of a general-purpose port and a 12-bit PPG output. Because its
buzzer output (BZ) function precedes the 12-bit PPG output function, if buzzer outputs are enabled, it
functions as the buzzer output (BZ) pin even if PPG outputs are enabled by the RCR23 (RCEN bit). To use
it as the 12-bit PPG output (PPG) pin, turn the buzzer outputs OFF.
● Limitation of "H" width setting
Using the "H" width setting bits of the 12-bit PPG control registers 1 and 2 (RCR21:HSC5 to HSC0 and
RCR22:HSC11 to HSC6), set a value that falls within the range of "000000000001
B
" to "111111111111
B
"
(001
H
to FFF
H
). If "000
H
" is set, "H" level outputs are delivered through the PPG pin. Furthermore, set the
value of the "H" width so as to be smaller than the value given by the cycle period setting bits of 12-bit
PPG control registers 3 and 4 (RCR23:SCL5 to SCL0 and RCR24:SCL11 to SCL6). If the "H" width is
equal to or greater than the cycle period, "H" level outputs are always delivered through the PPG pin.
● Resolution
When the cycle period is set at "111111111111
B
" (FFF
H
), a maximum "H" width resolution of 1/4095 is
obtained. This resolution is reduced as the cycle period setting becomes smaller and limited to a minimum
of 1/2 when the cycle period is set at "000000000010
B
" (002
H
).
● Setting change during operation
The "H" width setting bits (RCR21:HSC5 to HSC0 and RCR22:HSC11 to HSC6) and the cycle period
setting bits (RCR23:SCL5 to SCL0 and RCR24:SCL11 to SCL6) are compared with the 12-bit counter for
generating a frequency of 12-bit PPG waveforms. If the set values given by these bits are changed to
smaller values during the operation of the counter, a counter overflow occurs, which may extend the cycle
period until synchronization with a count by the counter is detected again. Similarly, this may extend the
"H" width until synchronization with a count by the counter is detected in the next cycle (cycle period).
Figure 9.6-1 illustrates setting change during the operation of the 12-bit PPG timer.