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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 97
FR81 Family
CHAPTER 6 INSTRUCTION OVERVIEW
6.5
6.5 Branching Instructions and Delay Slot
FR81 Family CPU Branching Instructions are of two types namely, Delayed Branching
Instructions and Non-delayed Branching Instructions.
6.5.1 Delayed Branching Instructions
In case of Delayed Branching Instructions, prior to execution of Branching Destination Instructions,
instructions immediately after Branching Instructions are executed. Instructions immediately after Delayed
Branching Instructions are called Delay slot.
Branching Instructions having ":D" affixed to mnemonic are Delayed Branching Instructions. Next
Instruction will be Delayed Branching Instruction.
JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D
BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9
BC:D label9 BNC:D label9 BN:D label9 BP:D label9
BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9
BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9
Since Delay Slot instructions are executed prior to Branching operation, apparent execution cycle of
Branching Instruction will be 1 cycle. In case a valid instruction cannot be allocated in the Delay slot, it is
necessary to allocate NOP Instruction. Example of Delayed Branching Instruction has been given below.
; Instructions alignment
ADD R1,R2
BRA:D LABEL ; Branching Instructions
MOV R2,R3 ; Delay slot (Executed before Branching)
. . .
LABEL: ST R3,@R4 ; Branching Destination
In case of Conditional Branching Instruction, whether or not Branching conditions are established, Delay
slot instructions are executed.
Instructions that can be placed in the Delay slot are only those that satisfy following conditions. When an
attempt is made to execute an instruction that cannot be placed in the delay slot, an invalid instruction
exception occurs and the EIT processing is carried out.
• 1 cycle Instructions
• Those that are not Branching Instructions