Filter
Top Products
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 49
FR81 Family
CHAPTER 4 RESET AND "EIT" PROCESSING
4.4
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3C4
H
) → PC
5. A new EIT event is detected.
The address saved to the system stack as a program counter (PC) value represents the instruction itself that
caused the undefined instruction exception. When a RETI instruction is executed, the contents of the
system stack should be rewritten with the exception processing routine so that the execution will either
resume from the address of the instruction next to the instruction that caused the exception.
4.4.2 Instruction Access Protection Violation Exception
An instruction access protection exception occurs when an instruction is executed in an area protected by
the memory protection function.
During debugging, this exception can be treated as a break source according to an indication from the
debugger. In this case, the instruction access protection violation exception does not occur.
Upon acceptance of the instruction access protection violation exception, the following operations take
place.
1. Transition to privilege mode is carried out, and the stack flag (S) is cleared.
"0" → UM "0" → S
2. The contents of the program status (PS) are saved to the system stack.
SSP - 4 → SSP PS → (SSP)
3. The contents of the program counter (PC) of an exception source instruction are saved to the system
stack.
SSP - 4 → SSP PC → (SSP)
4. The program counter (PC) value is updated by referring to the vector table.
(TBR + 3E4
H
) → PC
5. A new EIT event is detected.
4.4.3 Data Access Protection Violation Exception
A data access protection violation exception occurs when an invalid data access is executed in an area
protected by the memory protection function.
During debugging, this exception can be treated as a break source according to an indication from the
debugger. In this case, the data access protection violation exception does not occur.
If this exception occurs during data access with a RETI instruction in the process of an EIT sequence, the
CPU stops operating and is capable of accepting a reset and break interrupt.