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FR81 Family
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 469
MOV (Move Word Data in Program Status Register to
Destination Register)............................338
MOV (Move Word Data in Source Register to
Destination Register)............334, 336, 340
MOV (Move Word Data in Source Register to
Program Status Register) ......................342
Move
MOV (Move Word Data in Program Status Register to
Destination Register)............................338
MOV (Move Word Data in Source Register to
Destination Register)............334, 336, 340
MOV (Move Word Data in Source Register to
Program Status Register) ......................342
MSB
SRCH0 (Search First Zero bit position distance From
MSB) .................................................373
SRCH1 (Search First One bit position distance From
MSB) .................................................375
MUL
MUL (Multiply Word Data) ..............................346
MULH
MULH (Multiply Halfword Data) ......................348
Multiple
Multiple EIT Processing......................................60
Multiple EIT processing and Priority Levels..........60
Multiple Registers
LDM0 (Load Multiple Registers) .......................302
LDM1 (Load Multiple Registers) .......................304
STM0 (Store Multiple Registers) .......................410
STM1 (Store Multiple Registers) .......................412
Multiplication/Division Register
Multiplication/Division Register (MDH, MDL)
............................................................30
Multiply
MUL (Multiply Word Data) ..............................346
MULH (Multiply Halfword Data) ......................348
MULU (Multiply Unsigned Word Data) .............350
MULUH (Multiply Unsigned Halfword Data)
..........................................................352
MULU
MULU (Multiply Unsigned Word Data) .............350
MULUH
MULUH (Multiply Unsigned Halfword Data)
..........................................................352
N
NMI
Non-maskable Interrupts (NMI) ...........................55
No Operation
NOP (No Operation).........................................354
Non-block loading
Non-block loading ..............................................77
non-delayed branching
Example of branching with non-delayed branching
instructions ...........................................78
Non-Delayed Branching Instructions
Non-Delayed Branching Instructions....................99
Non-maskable Interrupts
Non-maskable Interrupts (NMI)...........................55
NOP
NOP (No Operation).........................................354
O
OR
BORH (Or 4bit Immediate Data to Higher 4bit of Byte
Data in Memory).................................149
BORL (Or 4bit Immediate Data to Lower 4bit of Byte
Data in Memory).................................151
OR (Or Word Data of Source Register to Data
in Memory).........................................356
OR (Or Word Data of Source Regis
ter to Destination
Register).............................................358
ORB
ORB (Or Byte Data of Source Register to Data
in Memory).........................................360
ORCCR
ORCCR (Or Condition Code Register and Immediate
Data)..................................................362
ORH
ORH (Or Halfword Data of Source Register to Data
in Memory)........................................364
P
PC
Program Counter (PC) ........................................20
Pipeline
How to prevent mismatched pipeline conditions?
............................................................73
Instruction execution based on Pipeline ................70
Pipeline Operation and Interrupt Processing..........73
Pointer
ADDSP (Add Stack Pointer and Immediate Data)
..........................................................119
Post
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................193
DMOVB (Move Byte Data from Direct Address to
Post Increment Register Indirect Address)
..........................................................199
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................201