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CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 41
4.1 Reset ................................................................................................................................................ 42
4.2 Basic Operations in EIT Processing ................................................................................................. 43
4.2.1 Types of EIT Processing and Prior Preparation .......................................................................... 43
4.2.2 EIT Processing Sequence ........................................................................................................... 44
4.2.3 Recovery from EIT Processing .................................................................................................... 45
4.3 Processor Operation Status .............................................................................................................. 46
4.4 Exception Processing ....................................................................................................................... 48
4.4.1 Invalid Instruction Exception ........................................................................................................ 48
4.4.2 Instruction Access Protection Violation Exception ....................................................................... 49
4.4.3 Data Access Protection Violation Exception ................................................................................ 49
4.4.4 FPU Exception ............................................................................................................................. 50
4.4.5 Instruction Break .......................................................................................................................... 51
4.4.6 Guarded Access Break ................................................................................................................ 52
4.5 Interrupts ........................................................................................................................................... 53
4.5.1 General interrupts ........................................................................................................................ 53
4.5.2 Non-maskable Interrupts (NMI) ................................................................................................... 55
4.5.3 Break Interrupt ............................................................................................................................. 55
4.5.4 Data Access Error Interrupt ......................................................................................................... 56
4.6 Traps ................................................................................................................................................. 57
4.6.1 INT Instructions ........................................................................................................................... 57
4.6.2 INTE Instruction ........................................................................................................................... 57
4.6.3 Step Trace Traps ........................................................................................................................ 58
4.7 Multiple EIT processing and Priority Levels ...................................................................................... 60
4.7.1 Multiple EIT Processing ............................................................................................................... 60
4.7.2 Priority Levels of EIT Requests ................................................................................................... 61
4.7.3 EIT Acceptance when Branching Instruction is Executed ........................................................... 62
4.8 Timing When Register Settings Are Reflected ................................................................................. 63
4.8.1 Timing when the interrupt enable flag (I) is requested ................................................................ 63
4.8.2 Timing of Reflection of Interrupt Level Mask Register (ILM) ....................................................... 64
4.9 Usage Sequence of General Interrupts ............................................................................................ 65
4.9.1 Preparation while using general interrupts .................................................................................. 65
4.9.2 Processing during an Interrupt Processing Routine .................................................................... 66
4.9.3 Points of Caution while using General Interrupts ........................................................................ 66
4.10 Precautions ....................................................................................................................................... 67
4.10.1 Exceptions in EIT Sequence and RETI Sequence ...................................................................... 67
4.10.2 Exceptions in Multiple Load and Multiple Store Instructions ....................................................... 67
4.10.3 Exceptions in Direct Address Transfer Instruction ....................................................................... 67
CHAPTER 5 PIPELINE OPERATION ............................................................................. 69
5.1 Instruction execution based on Pipeline ........................................................................................... 70
5.1.1 Integer Pipeline ............................................................................................................................ 70
5.1.2 Floating Point Pipeline ................................................................................................................. 72
5.2 Pipeline Operation and Interrupt Processing .................................................................................... 73
5.2.1 Mismatch in Acceptance and Cancellation of Interrupt ............................................................... 73
5.2.2 Method of preventing the mismatched pipeline conditions .......................................................... 73
5.3 Pipeline hazards ............................................................................................................................... 74