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CONTENTS
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU ............................................................ 1
1.1 Features of FR81 Family CPU ............................................................................................................ 2
1.2 Changes from the earlier FR Family ................................................................................................... 4
CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 7
2.1 Address Space ................................................................................................................................... 8
2.1.1 Direct Address Area ..................................................................................................................... 8
2.1.2 Vector Table Area .......................................................................................................................... 9
2.1.3 20-bit Addressing Area & 32-bit Addressing Area ....................................................................... 11
2.2 Data Structure ................................................................................................................................... 12
2.2.1 Byte Data ..................................................................................................................................... 12
2.2.2 Half Word Data ............................................................................................................................ 12
2.2.3 Word Data ................................................................................................................................... 12
2.2.4 Byte Order ................................................................................................................................... 13
2.3 Word Alignment ................................................................................................................................ 14
2.3.1 Program Access ......................................................................................................................... 14
2.3.2 Data Access ............................................................................................................................... 14
CHAPTER 3 PROGRAMMING MODEL .......................................................................... 15
3.1 Register Configuration ...................................................................................................................... 16
3.2 General-purpose Registers ............................................................................................................... 17
3.2.1 Configuration of General-purpose Registers ............................................................................... 17
3.2.2 Special Usage of General-purpose Registers ............................................................................ 18
3.2.3 Relation between Stack Pointer and R15 .................................................................................... 18
3.3 Dedicated Registers ......................................................................................................................... 19
3.3.1 Configuration of Dedicated Registers .......................................................................................... 19
3.3.2 Program Counter (PC) ................................................................................................................. 20
3.3.3 Program Status (PS) ................................................................................................................... 20
3.3.4 System Status Register (SSR) .................................................................................................... 21
3.3.5 Interrupt Level Mask Register (ILM) ............................................................................................ 22
3.3.6 Condition Code Register (CCR) .................................................................................................. 23
3.3.7 System Condition Code Register (SCR) .................................................................................... 25
3.3.8 Return Pointer (RP) ..................................................................................................................... 26
3.3.9 System Stack Pointer (SSP) ....................................................................................................... 27
3.3.10 User Stack Pointer (USP) ............................................................................................................ 28
3.3.11 Table Base Register (TBR) ......................................................................................................... 29
3.3.12 Multiplication/Division Register (MDH, MDL) ............................................................................... 30
3.3.13 Base Pointer (BP) ........................................................................................................................ 32
3.3.14 FPU Control Register (FCR) ........................................................................................................ 32
3.3.15 Exception status register (ESR) .................................................................................................. 37
3.3.16 Debug Register (DBR) ................................................................................................................. 39
3.4 Floating-point Register ...................................................................................................................... 40