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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 111
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.4
7.4 ADDC (Add Word Data of Source Register and Carry Bit to
Destination Register)
Adds word data and carry flag (C) of Rj to Ri, stores results in Ri.
● Assembler Format
ADDC Rj, Ri
● Operation
Ri + Rj + C → Ri
● Flag Change
N: Set when MSB of the operation result is "1", cleared when MSB is "0".
Z: Set when the operation result is zero, cleared otherwise.
V: Set when an overflow has occurred as a result of the operation, cleared otherwise.
C: Set when a carry has occurred as a result of the operation, cleared otherwise.
● Classification
Add/Subtract Instruction, Instruction with delay slot
● Execution Cycles
1 cycle
● Instruction Format
NZVC
CCCC
MSB LSB
10100111 Rj Ri