Filter
Top Products
FR81 Family
70 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 5 PIPELINE OPERATION
5.1
5.1 Instruction execution based on Pipeline
FR81 Family CPU processes a instruction using a pipeline operation. This makes it
possible to process to process nearly all instructions in one cycle. FR81 Family has two
pipelines: an integer pipeline and floating point pipeline.
Pipeline operation divides each type of step that carries out interpretation and execution of instructions of
CPU in to stages, and simultaneously executes different stages of each instruction. Instruction execution
that requires multiple cycles in other processing methods is apparently conducted in one cycle here.
Processing of both the integer pipeline and floating point pipeline are common up to the decoding stage,
and independent processing is carried out for each pipeline from the execution and subsequent stages. The
process sequence for each pipeline differs from the sequence of issuing instructions. However, the
processing result that has been acquired by following the program sequence procedure is guaranteed.
5.1.1 Integer Pipeline
Integer pipeline is a 5-stage pipeline compatible with FR family. A 4-stage load buffer is provided for non-
blocking loading.
The integer pipeline has the following 5-stage configuration.
• IF Stage: Fetch Instruction
Instruction address is generated and instruction is fetched.
• ID Stage: Decode Instruction
Fetched instruction is decoded. Register reading is also carried out.
• EX Stage: Execute Instruction
Computation is executed.
• MA Stage: Memory Access
Loading or access to storage is executed against the memory.
• WB Stage: Write Back to register
Computation result (or loaded memory data) is written in the register.
Example of the integer pipeline operation (1) is shown in Figure 5.1-1 and Example of integer pipeline
operation (2) is shown in Figure 5.1-2.