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CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 407
FR81 Family
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.164
7.164 STH (Store Halfword Data in Register to Memory)
Loads the half word data in Ri to memory address BP+u16 × 2. Unsigned u16 value is
calculated. The value in u16 × 2 is specified as udisp17.
● Assembler Format
STB Ri, @(BP, udisp17)
● Operation
Ri → (BP+u16 × 2)
● Flag Change
N, Z, V, C: Unchanged.
● Classification
Memory Store instruction, FR81 family
● Execution Cycles
a cycle
● Instruction Format
● EIT Occurrence and Detection
A data access protection violation exception, an invalid instruction exception (data access error), or an
interrupt is detected.
NZVC
----
MSB LSB
(n+0)000101110101 Ri
(n+2) u16