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46 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 4 RESET AND "EIT" PROCESSING
4.3
4.3 Processor Operation Status
Processor operation is comprised of four states: Reset, normal operation, low-power
consumption, and debugging.
● Reset state
A state where the CPU is being reset. Two levels are provided for the reset state: Initialize level and reset
level. When an initialize level reset is issued, all functions inside the MCU chip are initialized. When a
reset level is issued, functions except debug control, and some parts of the clock and reset controls are
initialized.
● Normal operation state
A state where the sequential instructions and EIT processing are currently executed. Privilege mode
(UM=0) and user mode (UM=1) are provided for the normal operation state. Some instructions and access
destinations are disabled in user mode while they are enabled in privilege mode.
After release of a reset state, the system enters privilege mode in the normal operation state, and is shifted
to user mode by executing a RETI instruction. In the normal operation state, user mode is shifted to
privilege mode by executing reset or EIT, and privilege mode is shifted to user mode by executing a RETI
instruction.
● Low-power consumption stat
A state where the CPU stops operating to save power consumption. Transition to the lower power
consumption state is carried out by controlling the stand-by in the clock control section. Three modes are
provided for the low-power consumption state: Sleep, stop and clock. An interrupt shall be used to restore
the system from the low-power consumption state.
● Debugging state
A state where an in-circuit emulator (ICE) is connected, and debug related functions are enabled. The
debugging state is separated into a user state and a debug state. In principle, a debugging state shall be
shifted to the other state via a reset. However, a normal operation state can be forcibly shifted to a
debugging state.
As is the case with the normal operation state, privilege mode (UM=0) and user mode (UM=1) are
provided for the user state. However, when a break is executed for debugging the state is shifted to the
debug state. It is carried out in privilege mode under the debug state, and all registers and whole memory
area can be accessed by disabling the memory protection and other functions. The debug state is shifted to
the user state by executing a RETI instruction.
Figure 4.3-1 shows transition between the processor operation states.