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458 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
APPENDIX
APPENDIX C Supplemental Explanation about FPU Exception Processing
[FCR:EEF:X=0]
The calculation result is stored in the floating point register.
The FCR:ECF:X flag is set.
6. Unnormalized Number Input exception (Denormalized Number Input)
This exception occurs when an unnormalized number is specified in the input operand. If this exception
occurs, the following operations are carried out.
[FCR:EEF:D=1]
Writing to the floating point register is prohibited.
The FCR:CEF:D flag is set to generate this exception.
[FCR.EEF.D=0]
The input operand that is set to an unnormalized number is flushed to zero before calculation.
The FCR:ECF:D flag is set.
C.3 Round Processing
Rounding processing conforms to IEEE754. A significand is expressed by 24 bits (single-precision). If a
significand of calculation result is expressed by the number of bits greater than 24 bits (including
unnormalized numbers), round processing is performed to obtain the approximate value of 24 bits (single-
precision). The following explains round processing.
The calculation result (S) of the significand is defined as follows (see next if the guard bit is omitted
(already processed)).
Figure C.3-1 Calculation Result of Significand including Guard Bit
Here, "g" indicates a guard bit, "r" indicates a round bit, "s" indicates a sticky bit, and "p" indicates a
significand.
Next, obtain the OR value (r∪s) between "r" and "s". Then set the result as "s" and set "g" as "r" again.
Figure C.3-2 Calculation Result of Significand omitting Guard Bit
Perform round processing based on the following Table C.3-1. Here, "S" indicates the calculation result of
the significand, "r" indicates a round bit, "s" indicates a sticky bit, and "LSB" indicates the LSB of "p".
("!s" indicates the reversal value of "s".)
26 3210
significand (p) g r s
25 210
significand (p) r s