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5.3.1 Occurrence of data hazard .......................................................................................................... 74
5.3.2 Register Bypassing ...................................................................................................................... 74
5.3.3 Interlocking .................................................................................................................................. 75
5.3.4 Interlocking produced by reference to R15 after Changing the Stack flag (S) ............................ 75
5.3.5 Structural Hazard ......................................................................................................................... 75
5.3.6 Control Hazard ............................................................................................................................ 76
5.4 Non-block loading ............................................................................................................................. 77
5.5 Delayed branching processing ......................................................................................................... 78
5.5.1 Example of branching with non-delayed branching instructions .................................................. 78
5.5.2 Example of processing of delayed branching instruction ............................................................ 79
CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 81
6.1 Instruction System ............................................................................................................................ 82
6.1.1 Integer Type Instructions ............................................................................................................. 82
6.1.2 Floating Point Type Instructions .................................................................................................. 84
6.2 Instructions Formats ......................................................................................................................... 85
6.2.1 Instructions Notation Formats ...................................................................................................... 85
6.2.2 Addressing Formats .................................................................................................................... 86
6.2.3 Instruction Formats ...................................................................................................................... 87
6.2.4 Register designated Field ............................................................................................................ 91
6.3 Data Format ...................................................................................................................................... 93
6.3.1 Data Format Used by Integer Type Instructions (Common with All FR Family) .......................... 93
6.3.2 Format Used for Floating Point Type Instructions ....................................................................... 94
6.4 Read-Modify-Write type Instructions ................................................................................................. 96
6.5 Branching Instructions and Delay Slot .............................................................................................. 97
6.5.1 Delayed Branching Instructions ................................................................................................... 97
6.5.2 Specific example of Delayed Branching Instructions ................................................................... 98
6.5.3 Non-Delayed Branching Instructions ........................................................................................... 99
6.6 Step Division Instructions ............................................................................................................... 100
6.6.1 Signed Division .......................................................................................................................... 100
6.6.2 Unsigned Division ...................................................................................................................... 101
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS .............................................. 103
7.1 ADD (Add 4bit Immediate Data to Destination Register) ................................................................ 105
7.2 ADD (Add Word Data of Source Register to Destination Register) ................................................ 107
7.3 ADD2 (Add 4bit Immediate Data to Destination Register) .............................................................. 109
7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ....................... 111
7.5 ADDN (Add Immediate Data to Destination Register) .................................................................... 113
7.6 ADDN (Add Word Data of Source Register to Destination Register) ............................................. 115
7.7 ADDN2 (Add Immediate Data to Destination Register) .................................................................. 117
7.8 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 119
7.9 AND (And Word Data of Source Register to Data in Memory) ....................................................... 121
7.10 AND (And Word Data of Source Register to Destination Register) ................................................ 123
7.11 ANDB (And Byte Data of Source Register to Data in Memory) ...................................................... 125
7.12 ANDCCR (And Condition Code Register and Immediate Data) ..................................................... 127
7.13 ANDH (And Halfword Data of Source Register to Data in Memory) ............................................... 129
7.14 ASR (Arithmetic shift to the Right Direction) ................................................................................... 131