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98 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 6 INSTRUCTION OVERVIEW
6.5
• Instructions that do not affect the operation even when the order is changed
1 cycle Instructions are those where anyone variable namely 1, a, b, c, d is independently written in the
CYC Column of "A.2 Instruction Lists". (Instructions which have 2a or 1+b are not 1 cycle instructions).
List of instructions that can be placed in Delay Slot are indicated in "Appendix A.3".
EIT processing such as Step Trace Trap, general interrupt, NMI etc. cannot be accepted between Delayed
Branching Instructions and Delay Slot Instructions.
6.5.2 Specific example of Delayed Branching Instructions
Specific example of Delayed Branching Instruction is given below.
"JMP:D @Ri" Instruction, "CALL:D @Ri" Instruction
General-purpose register Ri referred to during JMP:D Instruction, CALL:D Instruction is not affected
by the Branching Destination Address even if Delay Slot Instruction updates Ri.
[Ex]
LDI:32 #Label,R0
JMP:D @R0 ; Branching in Label
LDI:8 #0,R0 ; Does not affect Branching Destination Address
. . .
RET:D Instruction
Return Pointer (RP) referred to by RET:D Instruction is not affected even if Delay Slot Instruction
updates the Return Pointer (RP).
[Ex]
RET:D ; Branching to address indicated by RP set prior to this
MOV R8,RP ; Not affected by Return Operation
. . .
Bcc:D Instructions
Flag of Condition Code Register (CCR) referred to by Bcc:D Instruction is not affected by Delay Slot
Instructions.
[Ex]
ADD #1,R0 ; Flag change
BC:D overflow ; Branching based on execution result of preceding ADD Instruction
ANDCCR #0 ; Updating of this flag does not affect Branching