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34 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 3 PROGRAMMING MODEL
3.3
■ Floating point exception enable flag (EEF)
Floating point exception enable flag (EEF) is a 6-bit register that enables exception occurrences of floating
point calculation. It lies between bit 17 and bit 12 of the FPU control register (FCR).
Figure 3.3-25 shows the bit configuration of the floating point exception enable flag (EEF).
Figure 3.3-25 Floating point exception enable flag (EEF) Bit Configuration
The content of each bit are described below.
[bit17] D : D flag
This is a unnormalized number input exception enable flag. When this bit has been set to "1", the
FPU exception occurs upon input of an unnormalized number. When this bit has been set to "0", the
unnormalized number is regarded as "0" for calculation purposes.
[bit16] X : X flag
This is an inexact exception enable flag. When this bit is set to "1" and an inexact has occurred in
the calculation result, FPU exception occurs. When this bit is set to "0", the value resulting from
rounding up is written in the register.
[bit15] U : U flag
This is an underflow exception enable flag. When this bit is set to "1" and an underflow has
occurred in the calculation result, FPU exception occurs. When this bit is set to "0", a value "0" is
written in the register.
[bit14] O : O flag
This is an overflow exception enable flag. When this bit is set to "1" and an overflow has occurred
in the calculation result, FPU exception occurs. When this bit is set to "0", ± ∞ or ± MAX is written
in the register in accordance with the rounding mode (RM).
[bit13] Z : Z flag
This is a division-by-zero exception enable flag. When this bit is set to "1" and division-by-zero is
carried out, FPU exception occurs. When this bit is set to "0", infinite (∞), which indicates that the
calculation has been carried out appropriately, is written in the register.
[bit12] V : V flag
This is an invalid calculation exception enable flag. When this bit is set to "1" and an invalid
calculation is carried out, FPU exception occurs When this bit is set to "0", QNaN is written in the
register in the calculation type instruction, ± MAX is written in the register in the conversion
instruction, and "1" (unordered) is set for the U flag of the floating point condition code (FCC) in
the compare instruction.
bit15 bit14bit17 bit16 bit13bit12
UXDOZV
Initial value
XXXXXX
B