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FR81 Family
466 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
FBcc
FBcc (Floating Point Conditional Branch)...........232
FBcc:D (Floating Point Conditional Branch
with Delay Slot) ..................................234
FCMPs
FCMPs (Single Precision Floating Point Compare)
..........................................................236
FDIVs
FDIVs (Single Precision Floating Point Division)
..........................................................238
First One bit
SRCH1 (Search First One bit position distance From
MSB) .................................................375
First Zero bit
SRCH0 (Search First Zero bit position distance From
MSB) .................................................373
FiTOs
FiTOs (Convert from Integer to Single Precision
Floating Point).....................................240
flag
Timing when the interrupt enable flag (I) is requested
............................................................63
FLD
FLD (Load Word Data in Memory to Floating
Register) .............................................247
FLD (Single Precision Floating Point Data Load)
..........................242, 243, 244, 245, 246
FLDM
FLDM (Single Precision Floating Point Data Load to
Multiple Register)................................248
FMADDs
FMADDs (Single Precision Floating Point Multiply
and Add).............................................250
FMOVs
FMOVs (Single Precision Floating Point Move)
..........................................................252
FMSUBs
FMSUBs (Single Precision Floating Point Multiply
and Subtract).......................................253
FMULs
FMULs (Single Precision Floating Point Multiply)
..........................................................255
FNEGs
FNEGs (Single Precision Floating Point sign reverse)
..........................................................257
Format
Instruction Formats.............................................87
Formats
Addressing Formats ............................................86
Instructions Formats ...........................................85
Instructions Notation Formats ..............................85
FR Family
Changes from the earlier FR Family .......................4
FR81 Family
Features of FR81 Family CPU...............................2
FR81 Family CPU Register Configuration............16
FSQRTs
FSQRTs (Single Precision Floating Point Square
Root)..................................................258
FST
FST (Single Precision Floating Point Data Store)
..........................259, 260, 261, 262, 263
FST (Store Word Data in Floating Point Register to
Memory) ............................................264
FSTM
FSTM (Single Precision Floating Point Data Store
from Multiple Register) .......................265
FsTOi
FsTOi (Convert from Single Precision Floating Point
to Integer)...........................................267
FSUBs
FSUBs (Single Precision Floating Point Subtract)
..........................................................269
G
General Interrupt
General interrupts...
............................................53
General-purpose Registers
Configuration of General-purpose Registers..........17
General-purpose Registers...................................17
Interlocking produced by reference to R15 and
General-purpose Registers after Changing
the Stack flag (S flag) ............................75
Special Usage of General-purpose Registers .........18
H
Half Word Data
Half Word Data..................................................12
Halfword Data
ANDH (And Halfword Data of Source Register to
Data in Memory).................................129
DMOVH (Move Halfword Data from Direct Address
to Register).........................................203
DMOVH (Move Halfword Data from Direct Address
to Post Increment Register Indirect Address)
..........................................................207
DMOVH (Move Halfword Data from Post Increment
Register Indirect Address to Direct Address)
..........................................................209
DMOVH (Move Halfword Data from Register to
Direct Address)...................................205
EORH (Exclusive Or Halfword Data of Source
Register to Data in Memory) ................219
LDUH (Load Halfword Data in Memory to Register)
..........................................313, 315, 317
MULH (Multiply Halfword Data)......................348